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12th International Conference on Computer Communications and Networks (ICCCN 2003)

作者： Krishnamurthy, S Chandrasekaran, R Venkatesan, S Dawande, M Univ Texas Dept Comp Sci Richardson TX 75083 USA

ISBN: (纸本)0780379454

We consider the problem of spare capacity allocation in mesh networks for link restoration. Only single link failures are considered and restored traffic is not split across multiple paths. In our model, links that are not part of the original transport network can also be used for restoration. This model, which is a generalized version, is different from the traditional model studied in literature. We present two heuristics to solve this problem and compare their performance with known lower bounds and the optimal solution. In numerous simulation experiments on randomly generated graphs containing up to 100 nodes, the heuristics often produced solutions within 3% of the lower bound for sparse graphs. The integer linear programming solutions suggest that the heuristic solutions are closer to optimal than indicated by the deviation from the lower bounds. The results are optimal or near optimal (within 0.5% of the optimum values) for small graphs containing up to 8 nodes and 18 edges.

关键词： Bidirectional control Capacity planning Computer network management Computer science Costs integer linear programming Joining processes Mesh networks Telecommunication traffic Traffic control

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TESTLINE: An IEEE P1500 compatible test scheme for SoC test 5

TESTLINE: An IEEE P1500 compatible test scheme for SoC test

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5th International Conference on ASIC

作者： He, H Sun, YH Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China

ISBN: (纸本)078037889X

An IEEE P1500 compatible test scheme. TESTLINE, for modular SoC testing is presented in this paper. The test scheme consists of wrappers, TAM and User Defined Controller (UDC). For a given SoC, with specified parameters of modules and their tests, TESTLINE can optimize the testing time for the whole SoC using integer linear programming (ILP). The ILP can efficiently determine the width of TAM and the assignment of modules to TAM. Experimental results for the 'ITC '02 SOC Test Benchmarks' show that TESTLINE is an effective and efficient test scheme for SoC testing.

关键词： integer programming linear programming system-on-chip IEEE standards integrated circuit testing IEEE P1500 compatible test SoC test system-on-chip test TESTLINE UDC user defined controller ILP integer linear programming TAM test access mechanism

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An integrated optimization strategy for saving energy on multiprocessor-on-a-chip architectures

An integrated optimization strategy for saving energy on mul...

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IEEE International SOC Conference

作者： Chen, G Kandemir, M Kolcu, I Penn State Univ University Pk PA 16802 USA

ISBN: (纸本)0780381823

In an on-chip multiprocessor, there exist two major ways of saving energy: voltage scaling and processor shut-down. This paper makes a case for an integrated strategy where these two techniques are applied in concert for the best energy savings. We present an integer linear programming (ILP) approach that selects the best combination of voltage scaling and processor shut-down.

关键词： Banking Computer architecture Dynamic voltage scaling Energy consumption Frequency Hardware Hip integer linear programming linear programming USA Councils

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Peak power minimization through datapath scheduling

Peak power minimization through datapath scheduling

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IEEE-Computer-Society Annual Symposium on VLSI

作者： Mohanty, SP Ranganathan, N Chappidi, SK Univ S Florida Dept Comp Sci & Engn Nanomat & Nanomfg Res Ctr Tampa FL 33620 USA

ISBN: (纸本)0769519040

In this paper, we describe new integer linear programming models and algorithms for datapath scheduling that aim at minimizing peak power while maintaining performance. The first algorithm, MVDFC combines both multiple supply voltages and dynamic frequency clocking for peak power reduction, while the second algorithm, MVMC explores multiple supply voltages and multicycling. The algorithms use the number and type of different functional units at different operating voltages as the resource constraints. The effectiveness of the proposed scheduling algorithms is studied by estimating the peak power consumption and the power delay product (PDP) of the datapath circuit being synthesised. The algorithms have been applied to various high level synthesis benchmark circuits under different resource constraints. Experimental results show that for the MVDFC, under various resource constraints using two supply voltage levels (5.0V, 3.3V), average peak power reduction around 75% and average PDP reduction of 60% can be obtained. For the MVMC scheme, average peak power reduction is around 36% and average PDP reduction is 20%, for similar resource constraints.

关键词： Circuits Clocks Delay effects Delay estimation Energy consumption Frequency integer linear programming Minimization Scheduling algorithm Voltage

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Steiner tree construction based on congestion for the global routing problem 3

Steiner tree construction based on congestion for the global...

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3rd IEEE International Workshop on System-on-Chip for Real-Time Applications

作者： Behjat, L Vannelli, A Univ Calgary Dept Elect & Comp Engn Calgary AB Canada

ISBN: (纸本)076951944X

Global routing is an essential part of physical design, and has been traditionally formulated to minimize either an estimate of the total wirelength or the channel capacity of a circuit ignoring important issues such as congestion and number of bends. In this paper, a mathematical programming model that combines the wirelength minimization model and the channel capacity minimization model is presented. The combined model is also capable of incorporating different aspects of the global routing problem, such as via-count and congestion in two stages of the global routing problem: route construction and problem formulation. In addition, numerical enhancements have been proposed to increase the speed of the global routing formulation. Experiments on different benchmarks show that the new model builds a flexible and powerful technique that enhances the global routing solution compared to other mathematical programming techniques developed for global routing.

关键词： Channel capacity Circuits Design engineering integer linear programming Mathematical model Mathematical programming Minimization Physics computing Routing Very large scale integration

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Using multicriteria analysis to develop environmental flow scenarios for rivers targeted for water resource management

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WATER SA 2003年第4期29卷 365-374页

作者： Brown, CA Joubert, A Univ Cape Town Dept Zool So Waters Ecol Res & Consulting CC ZA-7705 Mowbray South Africa Univ Cape Town Dept Stat Sci ZA-7701 Rondebosch South Africa

DRIFT is an interactive, holistic approach for advising on environmental flows for rivers, The DRIFT methodology, together with multicriteria analysis (MCA), can be used to provide flow scenarios and descriptive summaries of their consequences in terms of the condition of the river ecosystem, for examination and comparison by decision-makers. The essential features of DRIFT, the output of workshops where it is applied, and the development of the DRIFT database are described. Modules within the database include DRIFTSOLVER and DRIFTCATEGORY. DRIFTSOLVER contains an integer linear programming MCA method, which generates optimally distributed flow scenarios for different total annual volumes of water. DRIFT CATEGORY facilitates evaluation of these in terms of river condition. These two modules are explained in detail and illustrated with examples.

关键词： environmental flows interactive holistic approach DRIFT multicriteria analysis scenarios river condition integer linear programming

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Peak power minimization through datapath scheduling

Peak power minimization through datapath scheduling

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IEEE Computer Society Annual Symposium on VLSI

作者： S.P. Mohanty N. Ranganathan S.K. Chappidi Department of Computer Science and Engineering Nanomaterial and Nanomanufacturing Research Center University of South Florida Tampa FL USA

关键词： Voltage Scheduling algorithm Delay estimation Circuits Minimization integer linear programming Frequency Clocks Energy consumption Delay effects

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Finding least cost proofs using high order recurrent networks

Finding least cost proofs using high order recurrent network...

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International Joint Conference on Neural Networks (IJCNN)

作者： A.M. Abdelbar E.A.M. Andrews G.A. Tagliarini Department of Computer Science American University Cairo Egypt Department of Computer Science North Carolina State University Wilmington USA

Cost-based abduction (CBA) is an important AI formalism for representing knowledge under uncertainty. In this formalism, evidence to be explained is treated as a goal to be proven, proofs have costs based on how much needs to be assumed to complete the proof, and the set of assumptions needed to complete the least-cost proof are taken as the best explanation for the given evidence. The problem of finding the least-cost proof for a given CBA system is NP-hard and current techniques have exponential complexity in the worst case. Computational intelligence approaches to this problem have not been previously explored. In this paper, we show how high order recurrent networks can be used to find least-cost proofs for CBA instances. We describe experimental results on 80 CBA instances using networks of up to 68 neurons.

关键词： Costs Computer science Neurons Artificial intelligence Uncertainty Computational intelligence integer linear programming Bayesian methods Logic programming

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An enhanced passive testing tool for network protocols

An enhanced passive testing tool for network protocols

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International Conference on Computer Networks and Mobile Computing (ICCNMC)

作者： Dongluo Chen Jianping Wu Tan Ieong Chu Department of Computer Science Tsinghua University China

ISBN: (纸本)0769520332

We study passive testing on protocols to detect faults in network devices. An enhanced passive testing tool is developed using integer linear programming in determining the ranges of the variables. On-line pruning reveals the current configuration of the system and the transition covered. Network system monitoring is conducted in a formal and fine-granularity way.

关键词： Protocols System testing Fault detection integer linear programming Monitoring Automata Computer networks Computer science Probes Software tools

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An integrated optimization strategy for saving energy on multiprocessor-on-a-chip architectures

An integrated optimization strategy for saving energy on mul...

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IEEE International SOC Conference

作者： G. Chen M. Kandemir I. Kolcu CSE Department The Pennsylvania State University University Park USA Computation Department UMIST (University of Manchester Institute of Science and Technology) Manchester UK

ISBN: (纸本)0780381823

关键词： Energy consumption Dynamic voltage scaling Computer architecture Hardware Hip USA Councils integer linear programming linear programming Banking Frequency

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