We consider the problem of spare capacity allocation in mesh networks for link restoration. Only single link failures are considered and restored traffic is not split across multiple paths. In our model, links that ar...
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ISBN:
(纸本)0780379454
We consider the problem of spare capacity allocation in mesh networks for link restoration. Only single link failures are considered and restored traffic is not split across multiple paths. In our model, links that are not part of the original transport network can also be used for restoration. This model, which is a generalized version, is different from the traditional model studied in literature. We present two heuristics to solve this problem and compare their performance with known lower bounds and the optimal solution. In numerous simulation experiments on randomly generated graphs containing up to 100 nodes, the heuristics often produced solutions within 3% of the lower bound for sparse graphs. The integer linear programming solutions suggest that the heuristic solutions are closer to optimal than indicated by the deviation from the lower bounds. The results are optimal or near optimal (within 0.5% of the optimum values) for small graphs containing up to 8 nodes and 18 edges.
In this paper, we describe new integer linear programming models and algorithms for datapath scheduling that aim at minimizing peak power while maintaining performance. The first algorithm, MVDFC combines both multipl...
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ISBN:
(纸本)0769519040
In this paper, we describe new integer linear programming models and algorithms for datapath scheduling that aim at minimizing peak power while maintaining performance. The first algorithm, MVDFC combines both multiple supply voltages and dynamic frequency clocking for peak power reduction, while the second algorithm, MVMC explores multiple supply voltages and multicycling. The algorithms use the number and type of different functional units at different operating voltages as the resource constraints. The effectiveness of the proposed scheduling algorithms is studied by estimating the peak power consumption and the power delay product (PDP) of the datapath circuit being synthesised. The algorithms have been applied to various high level synthesis benchmark circuits under different resource constraints. Experimental results show that for the MVDFC, under various resource constraints using two supply voltage levels (5.0V, 3.3V), average peak power reduction around 75% and average PDP reduction of 60% can be obtained. For the MVMC scheme, average peak power reduction is around 36% and average PDP reduction is 20%, for similar resource constraints.
In an on-chip multiprocessor, there exist two major ways of saving energy: voltage scaling and processor shut-down. This paper makes a case for an integrated strategy where these two techniques are applied in concert ...
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ISBN:
(纸本)0780381823
In an on-chip multiprocessor, there exist two major ways of saving energy: voltage scaling and processor shut-down. This paper makes a case for an integrated strategy where these two techniques are applied in concert for the best energy savings. We present an integer linear programming (ILP) approach that selects the best combination of voltage scaling and processor shut-down.
We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linearprogramming (ILP) for register allocation, optimal bank assignment, and spills. The compil...
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We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linearprogramming (ILP) for register allocation, optimal bank assignment, and spills. The compiler's optimizer employs CPS as its intermediate representation;some of the invariants that this IR guarantees are essential for the formulation of a practical ILP model. Appel and George used a similar ILP-based technique for the IA32 to decide which variables reside in registers but deferred the actual assignment of colors to a later phase. We demonstrate how to carry over their idea to an architecture with many more banks, register aggregates, variables with multiple simultaneous register assignments, and, very importantly, one where bank- and register-assignment cannot be done in isolation from each other. Our approach performs well in practise-without causing an explosion in size or solve time of the generated integerlinear programs.
In this paper, we describe new integer linear programming models and algorithms for datapath scheduling that aim at minimizing peak power while maintaining performance. The first algorithm, MVDFC combines both multipl...
详细信息
In this paper, we describe new integer linear programming models and algorithms for datapath scheduling that aim at minimizing peak power while maintaining performance. The first algorithm, MVDFC combines both multiple supply voltages and dynamic frequency clocking for peak power reduction, while the second algorithm, MVMC explores multiple supply voltages and multicycling. The algorithms use the number and type of different functional units at different operating voltages as the resource constraints. The effectiveness of the proposed scheduling algorithms is studied by estimating the peak power consumption and the power delay product (PDP) of the datapath circuit being synthesised. The algorithms have been applied to various high level synthesis benchmark circuits under different resource constraints. Experimental results show that for the MVDFC, under various resource constraints using two supply voltage levels (5.0V, 3.3V), average peak power reduction around 75% and average PDP reduction of 60% can be obtained. For the MVMC scheme, average peak power reduction is around 36% and average PDP reduction is 20%, for similar resource constraints.
Global market today demands rapid introduction of products while maintaining high quality and minimal costs. To accomplish the goals in a timely and efficient manner, companies are considering the power of collaborati...
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ISBN:
(纸本)0780379527
Global market today demands rapid introduction of products while maintaining high quality and minimal costs. To accomplish the goals in a timely and efficient manner, companies are considering the power of collaboration across the product lifecycle. This paper proposes a fuzzy decision guided method to optimize the component supplier selection in a dynamic collaborative environment. An objective function is advanced to formalize the component supplier selection problem. Fuzzy factors, fuzzy decision of the selection and their relations are analyzed. A fuzzy decisions based optimization algorithm is developed to select a set of suppliers that can provide the components at low prices and in time.
In an on-chip multiprocessor, there exist two major ways of saving energy: voltage scaling and processor shut-down. This paper makes a case for an integrated strategy where these two techniques are applied in concert ...
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ISBN:
(纸本)0780381823
In an on-chip multiprocessor, there exist two major ways of saving energy: voltage scaling and processor shut-down. This paper makes a case for an integrated strategy where these two techniques are applied in concert for the best energy savings. We present an integer linear programming (ILP) approach that selects the best combination of voltage scaling and processor shut-down.
Cost-based abduction (CBA) is an important AI formalism for representing knowledge under uncertainty. In this formalism, evidence to be explained is treated as a goal to be proven, proofs have costs based on how much ...
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Cost-based abduction (CBA) is an important AI formalism for representing knowledge under uncertainty. In this formalism, evidence to be explained is treated as a goal to be proven, proofs have costs based on how much needs to be assumed to complete the proof, and the set of assumptions needed to complete the least-cost proof are taken as the best explanation for the given evidence. The problem of finding the least-cost proof for a given CBA system is NP-hard and current techniques have exponential complexity in the worst case. Computational intelligence approaches to this problem have not been previously explored. In this paper, we show how high order recurrent networks can be used to find least-cost proofs for CBA instances. We describe experimental results on 80 CBA instances using networks of up to 68 neurons.
We study passive testing on protocols to detect faults in network devices. An enhanced passive testing tool is developed using integer linear programming in determining the ranges of the variables. On-line pruning rev...
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ISBN:
(纸本)0769520332
We study passive testing on protocols to detect faults in network devices. An enhanced passive testing tool is developed using integer linear programming in determining the ranges of the variables. On-line pruning reveals the current configuration of the system and the transition covered. Network system monitoring is conducted in a formal and fine-granularity way.
We present a new method for proving rank lower bounds for Cutting Planes (CP) and several procedures based on lifting due to Lovasz and Schrijver (LS), when viewed as proof systems for unsatisfiability. We apply this ...
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We present a new method for proving rank lower bounds for Cutting Planes (CP) and several procedures based on lifting due to Lovasz and Schrijver (LS), when viewed as proof systems for unsatisfiability. We apply this method to obtain the following new results: first, we prove near-optimal rank bounds for Cutting Planes and Lovasz-Schrijver proofs for several prominent unsatisfiable CNF examples, including random kCNF formulas and the Tseitin graph formulas. It follows from these lower bounds that a linear number of rounds of CP or LS procedures when applied to relaxations of integerlinear programs is not sufficient for reducing the integrality gap. Secondly, we give unsatisfiable examples that have constant rank CP and LS proofs but that require linear rank resolution proofs. Thirdly, we give examples where the CP rank is O(log n) but the LS rank is linear. Finally, we address the question of size versus rank: we show that, for both proof systems, rank does not accurately reflect proof size. Specifically, there are examples with polynomial-size CP/LS proofs, but requiring linear rank.
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