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IEEE Annual Joint Conference: INFOCOM, IEEE Computer and Communications Societies

作者： L. Gouveia P. Patricio A.F. de Sousa R. Valadas Department of Statistics and Operations Research Faculty of Sciences University of Lisbon Lisboa Portugal Institute of Telecommunications University of Aveiro Aveiro Portugal

MPLS (multiprotocol label switching) over WDM (wavelength division multiplexing) networks are gaining significant attention due to the efficiency in resource utilization that can be achieved by jointly considering the two network layers. This paper addresses the design of MPLS over WDM networks, where some of the WDM nodes may not have packet switching capabilities. Given the WDM network topology and the offered traffic matrix, which includes the location of the edge LSRs (label switched routers), we jointly determine the location of the core LSRs (i.e. the core WDM nodes that also need to include packet switching capabilities) and the lightpath routes (which are terminated on the LSRs) that minimize the total network cost. We consider constraints both at the optical and packet layers: an MPLS hop constraint on the maximum number of LSRs traversed by each LSP (label switched path), which guarantees a given packet level QoS, and a WDM path constraint on the maximum length of lightpaths, which accommodates the optical transmission impairments. A novel integer linear programming (ILP) formulation based on an hop-indexed approach, which we call the HOP model, is proposed. A two-phase heuristic, derived from a decomposition of the HOP model in two simpler ILP models that are solved sequentially, is also developed. The computational results show that the heuristic is efficient and produces good quality solutions, as assessed by the lower bounds computed from the HOP model. In some cases, the optimal solution is obtained with the branch-and-bound method.

关键词： Multiprotocol label switching WDM networks Wavelength division multiplexing Optical packet switching Packet switching Resource management Network topology Telecommunication traffic Costs integer linear programming

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Design of system-on-a-chip test access architectures using integer linear programming

Design of system-on-a-chip test access architectures using i...

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VLSI Test Symposium

作者： K. Chakrabarty Department of Electrical & Computer Engineering Duke University Durham NC USA

Test access is a major problem for system-on-a-chip (SOC) designs. Since embedded cores in an SOC are not directly accessible via chip I/Os, special access mechanisms are required to test them after system integration. An efficient test access architecture should reduce test cost and time-to-market by minimizing test application time. We address several issues related to the design of test access architectures. Even though these design problems are NP-complete, they can be solved exactly using integer linear programming (ILP). As a case study, the ILP models for two hypothetical but representative systems are solved using a public-domain ILP software package.

关键词： System-on-a-chip System testing integer linear programming Integrated circuit testing Bandwidth Costs Computer architecture Hip Operating systems Time to market

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A dynamic sectorization of microcells for balanced traffic in CDMA: Genetic algorithms approach

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IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 2002年第1期51卷 63-72页

作者： Lee, CY Kang, HG Park, T Korea Adv Inst Sci & Technol Dept Ind Engn Taejon 305701 South Korea Contela Inc Kyonggi Do 463783 South Korea

With the increase of cellular users, traffic hot spots and unbalanced call distributions are common in wireless networks. As a solution to this problem, code-division multiple-access techniques enable a base tranciever station to connect microcells with optical fibers and to control the channels by sectorizing the microcells. To solve the load balancing among microcells, we dynamically sectorize the microcells depending on the time-varying traffic. The microcell sectorization problem is formulated as an integer linear programming that minimizes the blocked and handoff calls in the network. In the proposed sectorization, proper, connected, and compact sectors are considered to keep the handoffs as small as possible while satisfying the channel capacity at each sector. Three genetic algorithms (GAs) are proposed to solve the problem: standard GA, grouping GA, and parallel GA. Computational results show that the proposed GAs are highly effective. All three GAs illustrate outstanding performance for small size problems. The parallel GA, which is based on the operators used in grouping GA, demonstrates excellent solution quality in a reasonable time.

关键词： Microcells sectorization Genetic Algorithm (GA) Load balancing integer linear programming Channel capacity handoff Gallium Traffic Code division multiple access

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Test bus sizing for system-on-a-chip

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IEEE TRANSACTIONS ON COMPUTERS 2002年第5期51卷 449-459页

作者： Iyengar, V Chakrabarty, K Duke Univ Dept Elect & Comp Engn Durham NC 27708 USA

System-on-a-chip (SOC) designs present a number of unique testability challenges to system integrators. Test access to embedded cores often requires dedicated test access mechanisms (TAMs). We present an improved approach for designing efficient TAMs and investigate the problems of improved deserialization of test data in the core wrapper, optimal test bus sizing, and optimal assignment of cores to test buses in the system. Place-and-route and power constraints are incorporated in the model. This work represents an important first step towards combining TAM design with efficient wrapper design for test data deserialization. Experimental results demonstrate that the proposed TAM optimization methodology provides efficient test bus designs for minimizing the testing time.

关键词： core-based systems embedded core testing integer linear programming linearization test access mechanism (TAM) test bus testing time

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Attacking the market split problem with lattice point enumeration

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JOURNAL OF COMBINATORIAL OPTIMIZATION 2002年第1期6卷 5-16页

作者： Wassermann, A Univ Bayreuth Math Inst D-95440 Bayreuth Germany

The market split problem was proposed by Cornuejols and Dawande as benchmark problem for algorithms solving linear systems with 0/1 variables. Here, we present an algorithm for the more general problem A . x = b with arbitrary lower and upper bound on the variables. The algorithm consists of exhaustive enumeration of all points of a suitable lattice which are contained in a given polyhedron. We present results for the feasibility version as well as for the integer programming version of the market split problem which indicate that the algorithm outperforms the previously published approaches to this problems considerably.

关键词： market split problem Diophantine linear systems lattice point enumeration lattice basis reduction integer linear programming subset sum problem

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Grid coverage for surveillance and target location in distributed sensor networks

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IEEE TRANSACTIONS ON COMPUTERS 2002年第12期51卷 1448-1453页

作者： Chakrabarty, K Iyengar, SS Qi, HR Cho, EC Duke Univ Dept Elect & Comp Engn Durham NC 27708 USA Kentucky State Univ Div Math & Sci Frankfort KY 40601 USA Univ Tennessee Dept Elect & Comp Engn Knoxville TN 37996 USA Louisiana State Univ Dept Comp Sci Baton Rouge LA 70803 USA

We present novel grid coverage strategies for effective surveillance and target location in distributed sensor networks. We represent the sensor field as a grid (two or three-dimensional) of points (coordinates) and use the term target location to refer to the problem of locating a target at a grid point at any instant in time. We first present an integer linear programming (ILP) solution for minimizing the cost of sensors for complete coverage of the sensor field. We solve the ILP model using a representative public-domain solver and present a divide-and-conquer approach for solving large problem instances. We then use the framework of identifying codes to determine sensor placement for unique target location. We provide coding-theoretic bounds on the number of sensors and present methods for determining their placement in the sensor field. We also show that grid-based sensor placement for single targets provides asymptotically complete (unambiguous) location of multiple targets in the grid.

关键词： covering codes identifying codes integer linear programming optimization sensor density sensor field

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A comparative analysis of several formulations for the generalized minimum spanning tree problem

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NETWORKS 2002年第1期39卷 29-34页

作者： Feremans, C Labbé, M Laporte, G Ecole Hautes Etud Commerciales Montreal PQ H3T 2A7 Canada Free Univ Brussels Serv Optimisat Inst Stat & Rech Operat B-1050 Brussels Belgium

This article describes eight formulations for the Generalized Minimum Spanning Tree Problem (GMSTP). Relationships between the polytopes of their linear relaxations are established. It is shown that four of these polytopes are strictly included in the remaining ones. This analysis suggests which formulations should be preferred for the construction of a branch-and-cut algorithm and for the evaluation of heuristics. (C) 2002 John Wiley Sons, Inc.

关键词： spanning trees integer linear programming polytopes

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On clique-transversals and clique-independent sets

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ANNALS OF OPERATIONS RESEARCH 2002年第1-4期116卷 71-77页

作者： Durán, G Lin, MC Szwarcfiter, JL Univ Buenos Aires Fac Ciencias Exactas & Nat Dept Computac Buenos Aires DF Argentina Univ Fed Rio de Janeiro BR-20001970 Rio De Janeiro Brazil Univ Fed Rio de Janeiro NCE Inst Matemat BR-20001970 Rio De Janeiro Brazil

A clique-transversal of a graph G is a subset of vertices intersecting all the cliques of G. A clique-independent set is a subset of pairwise disjoint cliques of G. Denote by tau(C)(G) and alpha(C)(G) the cardinalities of the minimum clique-transversal and maximum clique-independent set of G, respectively. Say that G is clique-perfect when tau(C)( H) = alpha(C)(H), for every induced subgraph H of G. In this paper, we prove that every graph not containing a 4-wheel nor a 3-fan as induced subgraphs and such that every odd cycle of length greater than 3 has a short chord is clique-perfect. The proof leads to polynomial time algorithms for finding the parameters tau(C)(G) and alpha(C)(G), for graphs belonging to this class. In addition, we prove that to decide whether or not a given subset of vertices of a graph is a clique-transversal is Co-NP-Complete. The complexity of this problem has been mentioned as unknown in the literature. Finally, we describe a family of highly clique-imperfect graphs, that is, a family of graphs G whose difference tau(C)(G) - alpha(C)(G) is arbitrarily large.

关键词： clique-independent sets clique-perfect graphs clique-transversals highly clique-imperfect graphs integer linear programming linear programming

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Test wrapper and test access mechanism co-optimization for system-on-chip

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2002年第2期18卷 213-230页

作者： Iyengar, V Chakrabarty, K Marinissen, EJ Duke Univ Dept Elect & Comp Engn Durham NC 27708 USA Philips Res Labs NL-5656 AA Eindhoven Netherlands

Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC.

关键词： embedded core testing test access mechanism (TAM) test wrapper testing time integer linear programming

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Low power memory design

Low power memory design

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13th IEEE International Conference on Applications-Specific Systems, Architectures and Processors

作者： Shiue, WT Oregon State Univ ECE Dept Corvallis OR 97331 USA

ISBN: (纸本)0769517129

In this paper, we present a novel design procedure for multi-module, multi-port memory design that satisfies area and/or energy/timing constraints. Our procedure consists of (i) use of Storage Bandwidth Optimization (SBO) techniques to simplify the conflict graph and (H) use of memory exploration techniques to determine the best memory configuration (number of modules, size and number of ports per module) with the minimum area if the energy and timing are bounded or with the minimum energy/timing if the area is bounded. Here the simplest conflict graph implies more possibilities for the arrays assigned to the same module without the penalty in an increase of the number of ports for each module. Our benchmark shows that the heuristic algorithm is very efficient to decide the best memory configuration for the system constraints (timing, area, or energy). In addition, the CACTI tool [14] is modified to estimate the timing, area, and energy for each module in different CMOS technologies (0. 8um. 0. 35um, and 0. 18um). Furthermore, we consider the lifetime for arrays;this results in the significant reduction in timing, area, and energy for the arrays executed in different cycles sharing the same memory module.

关键词： Bandwidth CMOS technology Concurrent computing Costs Delay Electrocardiography Energy storage Heuristic algorithms integer linear programming Timing

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