In this paper, we present a novel design procedure for multi-module, multi-port memory design that satisfies area and/or energy/timing constraints. Our procedure consists of (i) use of Storage Bandwidth Optimization (...
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ISBN:
(纸本)0769517129
In this paper, we present a novel design procedure for multi-module, multi-port memory design that satisfies area and/or energy/timing constraints. Our procedure consists of (i) use of Storage Bandwidth Optimization (SBO) techniques to simplify the conflict graph and (H) use of memory exploration techniques to determine the best memory configuration (number of modules, size and number of ports per module) with the minimum area if the energy and timing are bounded or with the minimum energy/timing if the area is bounded. Here the simplest conflict graph implies more possibilities for the arrays assigned to the same module without the penalty in an increase of the number of ports for each module. Our benchmark shows that the heuristic algorithm is very efficient to decide the best memory configuration for the system constraints (timing, area, or energy). In addition, the CACTI tool [14] is modified to estimate the timing, area, and energy for each module in different CMOS technologies (0. 8um. 0. 35um, and 0. 18um). Furthermore, we consider the lifetime for arrays;this results in the significant reduction in timing, area, and energy for the arrays executed in different cycles sharing the same memory module.
In WDM optical networks it is critical that lightpaths are routed in a way that a single link failure would not disconnect the network. We call such a routing survivable and develop algorithm for survivable routing of...
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ISBN:
(纸本)0780374908
In WDM optical networks it is critical that lightpaths are routed in a way that a single link failure would not disconnect the network. We call such a routing survivable and develop algorithm for survivable routing of a logical topology. We studied integer linear programming (ILP) formulation for the complete virtual topology design, including choice the, constituent lightpaths, routes for these lightpaths, and survivable.
Recently. researchers have proposed modeling register allocation as an integer linear programming (IP) problem and solving it optimally for general purpose processors [17, 20] and for dedicated embedded systems [23]. ...
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ISBN:
(纸本)0769518591
Recently. researchers have proposed modeling register allocation as an integer linear programming (IP) problem and solving it optimally for general purpose processors [17, 20] and for dedicated embedded systems [23]. Compared with traditional graph-coloring approaches, the IP-based allocators can improve a program's performance. However the solution times are much slower. This paper presents an IP-based optimal register allocator which is much faster than previous work. We present several local and global reduction techniques to identify locations in a program's control-flow graph where spill decisions and register deallocation decisions are unnecessary for optimal register allocation. We propose a hierarchical reduction approach to efficiently remove the corresponding redundant decisions and constraints front the IP model. This allocator is built into the Gnu C Compiler and is evaluated experimentally using the SPEC92INT benchmarks. The results show that the improved IP model is much simpler The number of constraints produced is almost linear with the function size. The optimal allocation time is much faster with a speedup factor of about 150 for hard allocation problems.
Most compilers ignore the problems of limited code space in embedded systems. Designers of embedded software often have no better alternative than to manually reduce the size of the source code or even the compiled co...
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ISBN:
(纸本)9781581135275
Most compilers ignore the problems of limited code space in embedded systems. Designers of embedded software often have no better alternative than to manually reduce the size of the source code or even the compiled code. Besides being tedious and error-prone, such optimization results in obfuscated code which is difficult to maintain and reuse. In this paper, we present a code-size-directed compiler. We phrase register allocation and code generation as an integer linear programming problem where the upper bound on the code size can simply be expressed as an additional constraint. Our experiments show that our compiler, when applied to two commercial microcontroller programs, generates code as compact as carefully crafted code.
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is therefore necessary for minimizing SOC tes...
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ISBN:
(纸本)0769515703
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is therefore necessary for minimizing SOC testing time. We recently proposed an exact technique for co-optimization based on a combination of integer linear programming (ILP) and exhaustive enumeration. However, this approach is computationally expensive for large SOCs, and it is limited to fixed-width test buses. We present a new approach for wrapper/TAM co-optimization based on generalized rectangle packing, also referred to as two-dimensional packing. This approach allows us to decrease testing time by reducing the mismatch between a core's test data needs and the width of the TAM to which it is assigned. We apply our co-optimization technique to an academic benchmark SOC and three industrial SOCs. Compared to the ILP-based technique, we obtain lower or comparable testing times for two out of the three industrial SOCs. Moreover, we obtain more than two orders of magnitude decrease in the CPU time needed for wrapper/TAM co-design.
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., eith...
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Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC.
It's well known, local scattering parts on a smooth convex object elements make the most important contribution to reflected signal energy. So these surface parts of complex shape objects are coated by radioabsorb...
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ISBN:
(纸本)078037391X
It's well known, local scattering parts on a smooth convex object elements make the most important contribution to reflected signal energy. So these surface parts of complex shape objects are coated by radioabsorbing materials (RM) in camouflage purpose. As a rule, the radioabsorbing coating (RC) has the sizeable weight and the, cost. In this, case the problem of optimal using of RM on the object surface has been occurred. The optimal coating method for the reduction of radar cross-sect ion (RCS) has been obtained for a certain illumination and reception directions in limitation conditions for a quantity of the RC using. Optimal coating has been realized due to decision of some integer linear programming problem. Using this method we have had RCS numerical results for reductive aircraft model partly coated by RM.
This paper presents a comprehensive investigation of a wide range of protection strategies against all single link failures in all-optical WDM networks based on mesh and multi-ring architectures. In the mesh architect...
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ISBN:
(纸本)488552184X
This paper presents a comprehensive investigation of a wide range of protection strategies against all single link failures in all-optical WDM networks based on mesh and multi-ring architectures. In the mesh architecture, three protection strategies, namely, minimal cost, single link basis and disjoint path protection strategies are investigated. In the multi-ring architecture, the distribution and non-distribution traffic multi-ring design strategies are extensively examined. Although, the concepts of mesh and multi-ring designs have previously been perceived to be fundamentally different, in this paper we shall explain and show that these two architectures can be systematically related and viewed as a unified concept. This new way of looking at the fully survivable network design helps understand clearly the mechanisms and performance of each protection strategy. To minimize the system cost of 100% protection WDM networks, mathematical models based on the integer linear programming (ILP) are derived as the tool for achieving optimal path placement, wavelength assignment and ring selection simultaneously. Apart from the mathematical model, the main contributions of this paper are the analysis and comparison in aspects of the spare capacity requirement and ease of operation and practical feasibility amongst these protection strategies. However, the emphasis will be on the multi-ring protection schemes. In addition, the influence of the number of multiplexed wavelengths per fiber to design outcomes and the benefit of having wavelength conversion capability in WDM network environment are also studied.
Array contraction is an optimization that transforms array variables into scalar variables within a loop. While the opposite transformation, scalar expansion, is used for enabling parallelism (with a penalty in memory...
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The Assistant Chief of Staff for Installation Management (ACSIM) manages all Army military construction (MILCON) implementation and requests. Annually, the ACSIM submits a prioritized list of MILCON projects requiring...
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The Assistant Chief of Staff for Installation Management (ACSIM) manages all Army military construction (MILCON) implementation and requests. Annually, the ACSIM submits a prioritized list of MILCON projects requiring Congressional approval. Typically, Congress does not approve all Army requests. This thesis develops an integerlinear program, PESA (Project Evaluation and Selection Assistant), to assist the ACSIM evaluate and select the best set of MILCON projects under various policies and budgets; thus assisting ACSIM develop a defendable set of MILCON projects to submit to Congress. Using a budget of $600 million (funds allocated in fiscal year 2001) and data for 62 projects for fiscal year 2001, we recommend funding a set of 50 projects that adhere to the following: fund each Major Army Command's projects in priority; limit each Major Army Command to less than 25% of the total budget; and use at least 80% of the total budget on the worst condition facilities. We demonstrate how this set of 50 projects better adheres to Army policies than those that would be recommended by the current Army technique.
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