In this paper we present a novel approach to find an optimum loop schedule under consideration of limited resources. The initiation interval λ is assumed to be a rational number. Our approach is formulated as a singl...
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In this paper, a test access mechanism named TESTLINE and its test time and power optimization algorithm for SOC test is presented. TESTLINE just needs 5 pins and can provide high-speed parallel test scheme. TESTLINE ...
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ISBN:
(纸本)0780366778
In this paper, a test access mechanism named TESTLINE and its test time and power optimization algorithm for SOC test is presented. TESTLINE just needs 5 pins and can provide high-speed parallel test scheme. TESTLINE has a scalable mechanism. Its schematic can be easily configured according to test time and test power. ILP (integer linear programming) is used to find the optimal results. TESTLINE also is a hierarchical Structure. It is easy to build a hierarchical test access mechanism.
In this paper, we present a novel and systematic approach for the design of shared memory architectures in the case of application-specific multiprocessor system-on-chip. This paper focuses on a memory allocation step...
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ISBN:
(纸本)1581134185
In this paper, we present a novel and systematic approach for the design of shared memory architectures in the case of application-specific multiprocessor system-on-chip. This paper focuses on a memory allocation step which is based on an integer linear programming model. It permits to obtain an optimal distributed shared memory architecture minimizing the global cost to access the shared data in the application, and the memory cost. Our approach allows automatic generation of an architecture-level specification of the application. The effectiveness of this approach is illustrated by a packet routing switch example.
To reduce domestic military infrastructure, the United States enacted two laws that instituted rounds of base realignment and closure (BRAC) in 1988, 1991, 1993, and 1995. As a result of these BRAC rounds, the United ...
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To reduce domestic military infrastructure, the United States enacted two laws that instituted rounds of base realignment and closure (BRAC) in 1988, 1991, 1993, and 1995. As a result of these BRAC rounds, the United States Army has closed or realigned 139 installations. Environmental cleanup is almost $2.3 billion (43%) of the entire cost associated with the closure and realignment of these 139 Army installations. The United States Army Base Realignment and Closure Office (BRACO) uses an integerlinear program called BAEC (Budget Allocation for Environmental Cleanup) to help determine how to allocate limited yearly funding to installations for environmental cleanup. Considering environmental policies and yearly installation funding requests from 2002 to 2015, this thesis modifies BAEC to better account for uncertainty in future environmental cleanup cost estimates. Based on historic data that show most environmental cleanup cost estimates increase over time, the stochastic BAEC model recommends funding fewer sites than the deterministic BAEC model recommends. The stochastic BAEC model thereby provides funding recommendations with a better chance of staying within limited available yearly funding.
It is not known if planar integer linear programming is P-complete or if it is in NC, and the same can be said about the computation of the remainder sequence of the Euclidean algorithm applied to two integers. Howeve...
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It is not known if planar integer linear programming is P-complete or if it is in NC, and the same can be said about the computation of the remainder sequence of the Euclidean algorithm applied to two integers. However, both computations are NC equivalent. The latter computational problem was reduced in NC to the former one by Deng [Mathematical programming: Complexity and Application, Ph.D. dissertation, Stanford University, Stanford, CA, 1989;Proc. ACM Symp. on Parallel Algorithms and Architectures, 1989, pp. 110-116]. We now prove the converse NC-reduction.
In this paper, an effective algorithm is proposed to generate crosstalk-reduced routing solutions, where nonmonotonic routing is allowed, for the gridded strait-type river routing (STRR) problem. Given an initial rout...
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In this paper, an effective algorithm is proposed to generate crosstalk-reduced routing solutions, where nonmonotonic routing is allowed, for the gridded strait-type river routing (STRR) problem. Given an initial routing solution generated by a conventional STRR algorithm, the reduction of crosstalks is carried out by the reassignment of the horizontal and vertical wire segments. Besides minimizing crosstalks, the minimization of the number of jogs is also considered in the reassignment process for performance promotion. To effectively and optimally perform the reassignment process, an integer linear programming (ILP) formulation is proposed. The experimental results show that this approach of ILP is very encouraging.
In this paper we concern ourselves with the problem of minimizing leakage power in CMOS circuits consisting of AOI (and-or-invert) gates as they operate in stand-by mode or an idle mode waiting for other circuits to c...
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ISBN:
(纸本)0769509932
In this paper we concern ourselves with the problem of minimizing leakage power in CMOS circuits consisting of AOI (and-or-invert) gates as they operate in stand-by mode or an idle mode waiting for other circuits to complete their operation. It is known that leakage power due to sub-threshold leakage current in transistors in the OFF state is dependent on the input vector applied. Therefore, we try to compute an input vector that can be applied to the circuit in stand-by mode so that the power loss due to sub-threshold leakage current is the minimum possible. We employ a integer linear programming (ILP) approach to solve the problem of minimizing leakage by first obtaining a good lower bound (estimate) on the minimum leakage power and then rounding the solution to actually obtain an input vector that causes low leakage. The chief advantage of this technique as opposed to others in the literature is that it invariably provides us with a good idea about the quality of the input vector found.
We present a novel and systematic approach for the design of shared memory architectures in the case of application-specific multiprocessor system-on-chip. This paper focuses on a memory allocation step which is based...
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We present a novel and systematic approach for the design of shared memory architectures in the case of application-specific multiprocessor system-on-chip. This paper focuses on a memory allocation step which is based on an integer linear programming model. It permits one to obtain an optimal distributed shared memory architecture minimizing the global cost to access the shared data in the application, and the memory cost. Our approach allows automatic generation of an architecture-level specification of the application. The effectiveness of this approach is illustrated by a packet routing switch example.
The authors present an approach that supports three phases of R&D project selection: proposal candidates are identified by a score based screening process; an integer linear programming model determines all effici...
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The authors present an approach that supports three phases of R&D project selection: proposal candidates are identified by a score based screening process; an integer linear programming model determines all efficient portfolios considering multiple objectives, project interdependencies, and time; and an interactive procedure matches portfolios with aspired benefit and resource levels.
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