检索结果-内蒙古大学图书馆

Using integer linear programming for instruction scheduling and register allocation in multi-issue processors

COMPUTERS & MATHEMATICS WITH APPLICATIONS 1997年第9期34卷 1-14页

作者： Chang, CM Chen, CM King, CT Department of Computer Science National Tsing Hua University Hsinchu Taiwan 300 R.O.C.

Instruction scheduling and register allocation are two very important optimizations in modern compilers for advanced processors. These two optimizations must be performed simultaneously in order to maximize the instruction-level parallelism and to fully utilize the registers [1]. In this paper, we solve register allocation and instruction scheduling simultaneously using integer linear programming (ILP). We have successfully worked out the ILP formulations for the problem with and without register spilling. Two kinds of optimizations are considered: (1) fix the number of free registers and then solve the minimum number of cycles to execute the instructions, or (2) fix the maximum execution cycles for the instructions and solve the minimum number of registers needed. Besides being theoretically interesting, our solution serves as a reference point for other heuristic solutions. The formulations are also applicable to high-level synthesis of ASICs and designs for embedded processors. In these application domains, the code quality is more important than the compilation time.

关键词： integer linear programming compiler optimization instruction scheduling register allocation processor architecture

来源：评论

学校读者我要写书评

暂无评论

Computing resource bounds using inclusion scheduling

Computing resource bounds using inclusion scheduling

引用

International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： C. Chantrapornchai S. Tongsima Dept. of Math. Silpakorn Univ. Nakorn Pathom Thailand HPCC Laboratory NECTEC Bangkok Thailand

We propose an framework to estimate resource bounds. The framework takes imprecise system characteristics and multiple design attributes into account. Considering a design goal, an initial bound is first generated. Then, a polynomial-time process called inclusion scheduling is used as a tool to determine a schedule under impreciseness and improve the bounds. Our experiments show that considering impreciseness can achieve a better bound than the traditional approach.

关键词： Processor scheduling Process design integer linear programming Mathematics Geometry Fabrication Time measurement High level synthesis Propagation delay Fuzzy set theory

来源：评论

学校读者我要写书评

暂无评论

Genetic algorithms for multiobjective scheduling of combined batch/continuous process plants

Genetic algorithms for multiobjective scheduling of combined...

引用

Congress on Evolutionary Computation

作者： K.J. Shaw P.L. Lee H.P. Nott M. Thompson School of Engineering Murdoch University Perth WA Australia CSIRO-Mathematical and Information Sciences VIC Australia Department of Engineering Sheffield Hallam University Sheffield UK

Systems in the process industry commonly incorporate both batch and continuous processes. These processes must be scheduled to satisfy product specifications, requirements from downstream processes and physical plant constraints. In doing so, the need to maximise various production objectives within a highly constrained environment can present an extremely difficult problem. This paper demonstrates the difficulties of attempting to schedule the combination of discrete tasks of varying cycle times with continuous elements. Two implementations of a heuristic genetic algorithm (GA) approach are demonstrated on a processing problem that has similar characteristics to a sugar mill. The implementations include problem-specific representations, single and multiobjective approaches to handle the four problem costs, and various uses of penalty functions to avoid constraint violations. In addition, highly tailored problem-specific operators allow the GA to match its behaviour to the critical elements in the problem definition, specifically those relating to a highly constrained shared storage facility. The results and implications of using such techniques for this type of problem are presented and discussed.

关键词： Genetic algorithms Job shop scheduling Optimal scheduling Sugar industry Australia Production Milling machines Cost function integer linear programming

来源：评论

学校读者我要写书评

暂无评论

Thread partitioning method for hardware compiler Bach

Thread partitioning method for hardware compiler Bach

引用

Asia and South Pacific Design Automation Conference

作者： M. Takahashi N. Ishiura A. Yamada T. Kambei Department of Information Systems Engineering Graduate School of Engineering Osaka University Suita Osaka Japan Design Technology Development Center IC group Sharp Corporation Tenri Nara Japan

This paper presents a method for thread partitioning for a hardware compiler Bach. Bach synthesizes RT level circuits from a system description written in Bach-C language, where a system is modeled as communicating processes running in parallel. The system description is decomposed into threads, i.e., strings of sequential processes, and then converted into synthesizable behavioral VHDL models. The proposed method attempts to find a partitioning of a given system description into threads that maximize resource sharing among processes in the threads. Experiments on two real designs show that the circuit sizes were reduced by 3.7% and 14.7%. We also show the detailed statistics and analysis of the size of the resulting gate level circuits.

关键词： Yarn Hardware Circuit synthesis Resource management Synthesizers integer linear programming Information systems Systems engineering and theory Statistical analysis Consumer products

来源：评论

学校读者我要写书评

暂无评论

A novel scheduler for low power real time systems

A novel scheduler for low power real time systems

引用

Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Wen-Tsong Shiue J. Denison A. Horak System Level Design ASP/SPS Motorola Inc. Austin TX USA

The work presented in this paper focuses on behavioral level power optimization. Specifically, we address the problem of scheduling a data-flow graph (DFG) under latency constraints. We have developed a revised integer linear program (ILP) model that minimizes both the peak power and the number of resources while satisfying timing constraints. Our modified integer linear programming (MILP) algorithm extends the traditional ILP approach, that minimizes, resources to include peak power considerations while adding extensions for multi-cycle and pipelined arithmetic components. To demonstrate the MILP algorithm's efficacy, two DFGs were examined: a second order differential equation solver (DiffEq) and a finite length impulse response filter (FIR). In our benchmark results, the peak power in DiffEq was reduced 25% after scheduling alone and reduced 50% after scheduling and pipelining were both applied. The FIR filter was reduced 63% after scheduling and reduced 75% after scheduling and pipelining.

关键词： Real time systems Libraries Voltage Clocks Delay System-level design Timing integer linear programming Finite impulse response filter Pipeline processing

来源：评论

学校读者我要写书评

暂无评论

Design partitioning on single-chip emulation systems

Design partitioning on single-chip emulation systems

引用

International Conference on VLSI Design

作者： A. Ejnioui N. Ranganathan Center for Microelectronics Research Department of CSE University of South Florida Tampa FL USA

ISBN: (纸本)0769504876

In this paper, we address the problem of partitioning a large design on a reconfigurable single-chip emulator under resource constraints. First, we extract an acyclic flow graph of the design to be emulated. Then, we model the problem as an integer linear programming problem (IP) based on the acyclic flow graph of the design where the structure of the assignment and precedence constraints produce a tight formulation. This formulation is suitable for small designs. For larger designs, we generate a smaller formulation of the integer programming problem based on a reduced form of the acylic graph. Then we use an incremental iterative technique to keep the problem formulation as small as possible. To partition a large design, our algorithm uses two distinct steps with different objectives. In the first step, we minimize the number of cycles needed to schedule every lookup table (LUT) in the circuit. Then flip-flops (FFs) are inserted into the appropriate cycles of the schedule in the second step. Experiments are conducted on small and moderately large circuits from the MCNC Partitioning93 benchmark suite. The obtained results show that our algorithm produces optimal partitioning schedules.

关键词： Emulation Flow graphs Partitioning algorithms Table lookup Circuits integer linear programming linear programming Algorithm design and analysis Iterative algorithms Flip-flops

来源：评论

学校读者我要写书评

暂无评论

Exploring risk management tools

Exploring risk management tools

引用

Proceedings of the IEEE/IAFE Computational Intelligence for Financial Engineering (CIFEr)

作者： Kah-Hoe Ng G.B. Sheble Department of Electrical and Computer Engineering Iowa State University Ames IA USA

Operations research tools vary significantly. In this paper, several operations research tools that can handle uncertainty are investigated. They include sensitivity analysis, parametric analysis, mean-variance analysis, stochastic linear programming, fuzzy linear programming, and value at risk (VaR). In addition, these tools are compared and contrasted based on their applicability, time, and technical requirements.

关键词： Risk management linear programming Operations research Sensitivity analysis Stochastic processes Risk analysis Vectors integer linear programming Costs Uncertainty

来源：评论

学校读者我要写书评

暂无评论

Representing and scheduling looping behavior symbolically

Representing and scheduling looping behavior symbolically

引用

IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： S. Haynal F. Brewer University of California Santa Barbara USA

This paper presents a very general, exact technique for scheduling looping data-flow graphs. In contrast to the conventional technique using loop iteration variables and integer linear programming, the new technique uses implicit symbolic automata techniques to represent the problem instance. The new technique has several advantages, such as incremental refinement, efficient variable usage and ability to accommodate practical design constraints. A small case study demonstrates the flexibility and viability of this technique.

关键词： Delay High level synthesis Protocols Pipeline processing Flow graphs integer linear programming Automata Hardware Potential well Timing

来源：评论

学校读者我要写书评

暂无评论

Water supply planning simulation model wing mixed-integer linear programming ''engine''

引用

JOURNAL OF WATER RESOURCES PLANNING AND MANAGEMENT-ASCE 1997年第2期123卷 116-124页

作者： Randall, D Cleland, L Kuehne, CS Link, GW Sheer, DP WATER RESOUR PLNG PROGRAM MGR FREMONTCA 94537 HYDROL CONSULTANTS INC DAVISCA 95616

This paper presents a simulation model to be used for water supply planning by a metropolitan water utility, Water supply operations for a single, monthly time step are formulated as a mixed integer linear program (or more simply, LP). The LP is then embedded in a month-by-month simulation model, The LP is formulated using a priority-based objective function, The model has been used successfully by the Alameda County Water District (California) staff for its long-range, integrated planning. The model also shows that some of the inherent weaknesses of math programming in general and mixed integer linear programming in particular, can be overcome to build a successful model.

关键词： System integer linear programming water utilities Integrated planning Simulation models Water districts linear programming Water Supply Mixed integer linear programming

来源：评论

学校读者我要写书评

暂无评论

Minimum crosstalk layer assignment in a three layer HVH channel routing based on linear pseudo Boolean optimization

Minimum crosstalk layer assignment in a three layer HVH chan...

引用

International Conference on Microelectronics, ICM

作者： Kyoung Jhang Department of Computer Engineering Hannam University Taejon South Korea

ISBN: (纸本)9643600572

Current deep-submicron VLSI technology appears to cause severe crosstalk problems, since it requires adjacent wires to be placed closer and closer together. This paper deals with a horizontal layer assignment problem for three layer HVH channel routing to minimize coupling capacitance, a main source of crosstalk. It is formulated in a 0/1 integer linear programming problem which is then solved by a linear pseudo Boolean optimization technique. Experiments show that our accurate upper bound estimation technique effectively reduces crosstalk in a reasonable amount of running time.

关键词： Crosstalk Routing Capacitance Wire Delay Polynomials Very large scale integration Coupling circuits integer linear programming Upper bound

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：