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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Joonyoung Kim J. Whittemore K. Sakallah Electrical Engineering and Computer Science Department University of Michigan USA

Boolean satisfiability (SAT) and its application to a number of electronic design automation (EDA) problems have been the topic of extensive study over the lost couple of decades. In many cases, a set of related SAT problems need to be solved in order to obtain an answer to a given application-specific problem. Incremental satisfiability (ISAT) refers to solving a set of related SAT problems by augmenting a previously solved problem with additional constraints, thereby reusing previous decision sequences. In this paper, we present a new ISAT engine that supports both the addition and removal of constraints. This can be achieved by keeping track of the relationships between constraints. We identify and define a special type of ISAT that occurs frequently in the context of path sensitization called stack-based ISAT and define the structure of this as a problem tree. In this type of ISAT constraints are allowed to be added and removed only in last-in first-out (LIFO) order. We also introduce a solution caching mechanism to expedite the search by recording and retrieving solutions to intermediate nodes in a problem tree.

关键词： Electronic design automation and methodology Engines Logic testing Application software Computer science Timing Electronic equipment testing Automatic testing Logic design integer linear programming

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Gate triggering: a new framework for minimizing glitch power dissipation in static CMOS ICs and its ILP-based optimization

Gate triggering: a new framework for minimizing glitch power...

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IEEE International Caracas Conference on Devices, Circuits and Systems

作者： N.R. Mahapatra R. Janakiraman Department of Computer Science & Engineering State University of New York University at Buffalo Buffalo NY USA

Glitches are an important source of power dissipation in static CMOS ICs that can contribute to as much as 70% of total power dissipation in certain cases (e.g., arithmetic modules). Although research into various aspects of glitch power dissipation has been undertaken in the past, most approaches to addressing it are ad hoc and limited in their applicability. In this paper, we propose a new framework, gate triggering, for systematically minimizing glitch power dissipation in static CMOSICs. The framework is based on the idea that glitches can be effectively minimized by triggering logic evaluation at a gate only when all of its inputs have stabilized. For this purpose, to every potentially glitchy gate is added a small amount of control logic, which, when enabled, triggers logic evaluation at the gate. A clocked delay chain is employed to generate enable signals at the proper times for all gates to be triggered. We present an integer linear programming (ILP) formulation to minimize the overheads (viz. delay element, control logic, and extra wiring) of our approach subject to a critical-path delay constraint. Application of the new approach to test circuits (such as ripple carry adder and array multiplier) in 1.2 /spl mu/ technology yields 95% or more elimination of glitch power dissipation with negligible area and timing overheads after optimization. An added advantage of the approach is that short-circuit power dissipation at all triggered gates is also minimized-short-circuit power dissipation in current standard-cell based designs can exceed 50% of the total power dissipation.

关键词： Power dissipation Logic programming Delay Circuit testing Arithmetic Clocks Signal generators integer linear programming Wiring Adders

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Fuzzy approaches to the production problems: the case of refinery industry

Fuzzy approaches to the production problems: the case of ref...

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International Conference on Information Fusion

作者： M. Gunes Department of Econometrics University of Dokuz Eylul Fac. of Econ. and Adm. Sciences Buca Izmir Turkey

The fuzzy principle states that everything is a matter of degree. So far, many business production problems are solved by operational research optimization techniques, under the considerations of some assumptions. In the current literature, we still have several applications of fuzzy linear, integer, goal and other programming applications. The main aim of the study is to add a new application to the literature and to solve the refinery production problem by using fuzzy principles. In application, the real refinery model has been developed and an alternative fuzzy model solution has been criticized to determine which one is better. Finally, comparing the classical solution with one of the obtained best solutions of the fuzzy models, one can obtain more suitable output of the models than the traditional methods.

关键词： Production Computer aided software engineering Refining linear programming Econometrics integer linear programming Fuzzy logic Multivalued logic Arithmetic Mathematical programming

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Product mix planning in semiconductor foundry manufacturing

Product mix planning in semiconductor foundry manufacturing

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Semiconductor Manufacturing Technology Workshop

作者： Y-C Chou Industrial Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)0780363744

Since a semiconductor foundry plant manufactures a wide range of memory and logic products using the make-to-order business model, the product mix is an important production decision. This paper first describes the characteristics of the product mix planning problem in foundry manufacturing that are attributable to the long flow time and queuing network behaviors. The issues of time bucket selection, mix optimization and bottleneck-based planning are next addressed. A decision software system based on integer linear programming techniques and a heuristic procedure have been implemented for mix planning. It was determined that the suitable time bucket of planning is either one week or one month and the lead-time offset factor should be included in the logic of workload calculation. This paper also presents various facets of product mix decisions and how they should be integrated with operations management.

关键词： Semiconductor device manufacture Capacity planning Foundries Logic Production integer linear programming Portfolios Process planning Cost accounting Aggregates

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A branch-first, cut-second approach for locomotive assignment

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MANAGEMENT SCIENCE 1999年第8期45卷 1156-1168页

作者： Ziarati, K Soumis, F Desrosiers, J Solomon, MM Ecole Polytech Dept Math & Genie Ind Montreal PQ H3C 3A7 Canada Gerad Montreal PQ H3T 2A7 Canada Ecole Hautes Etud Commerciales Montreal PQ H3T 2A7 Canada Northeastern Univ Coll Business Adm Dept Management Sci Boston MA 02115 USA

The problem of assigning locomotives to trains consists of selecting the types and number of engines that minimize the fixed and operational locomotive costs resulting from providing sufficient power to pull trains on fixed schedules. The force required to gull a train is often expressed in terms of horsepower and tonnage requirements rather than in terms of number of engines. This complicates the solution process of the integer programming formulation and usually creates a large integrality gap. Furthermore, the solution of the linearly relaxed problem is strongly fractional. To obtain integer solutions, we propose a novel branch-and-cut approach. The core of the method consists of branching decisions that define on one branch the projection of the problem on a low-dimensional subspace. There, the facets of the polyhedron describing a restricted constraint set can be easily derived. We call this approach branch-fil st, cut-second. We first derive facets when at most two types of engines are used. We then extend the branching rule to cases involving additional locomotive types. We have conducted computational experiments using actual data from the Canadian National railway company. Simulated test-problems involving two or more locomotive types were solved over 1-, 2-, and 3-day rolling horizons. The cuts were successful in reducing the average integrality gap by 52% for the two-type case and by 34% when more than 25 types were used. Furthermore, the branch-first, cut-second approach was instrumental in improving the best known solution for an almost 2,000-leg weekly problem involving 26 locomotive types. It reduced the number of locomotives by 11, or 1.1%, at an equivalent savings of $3,000,000 per unit. Additional tests on different weekly data produced almost identical results.

关键词： integer linear programming branch and cut decomposition scheduling railway

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Group coancestry-controlled selection in a Pinus sylvestris L. breeding program

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THEORETICAL AND APPLIED GENETICS 1999年第1-2期99卷 73-80页

作者： Andersson, EW Rodríguez, LS Andersson, B Swedish Univ Agr Sci Dept Forest Genet & Plant Physiol S-90183 Umea Sweden Forestry Res Inst Sweden S-91821 Savar Sweden

integer linear programming was used to maximize genetic gain from selection at a given level of relatedness. Variances and breeding values for total height were available for 296 plus-trees of Pinus sylvestris which had been evaluated by open-pollinated progeny testing at a single test site in northern Sweden. Second-generation breeding and selection scenarios far this breeding population were evaluated using simulated data derived deterministically from normal distributions of estimated breeding values of progeny around mid-parent family means. The study considered two mating designs, assortative and non-assortative single-pair mating, and two selection criteria, individual phenotype and performance of half-sib progeny. Relatedness (group coancestry) was restricted to a level equivalent to that given by within-family selection of 2 trees per family from each of 25 families (the current standard in Sweden). Selection that allows the best-performing families to contribute a greater number of progeny was superior, both when the breeding population size was limited to 50 individuals and when it was allowed to be larger. The selected set giving the greatest average breeding value under restricted group coancestry included the best individual from families that would have been rejected under application of standard within-family selection. We made a comparison of the present value on retrieved gain between phenotypic selection and evaluation by progeny testing.

关键词： breeding program coancestry genetic diversity group coancestry integer linear programming selection

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Retiming control logic

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INTEGRATION-THE VLSI JOURNAL 1999年第1期28卷 33-53页

作者： Maheshwari, N Sapatnekar, SS Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA Iowa State Univ Dept Elect & Comp Engn Ames IA 50011 USA

Retiming is a powerful technique for delay and area optimization that operates by relocating the flip-flops in a circuit. This movement of flip-flops in control logic changes the state encoding of finite state machines, requiring the preservation of initial (reset) states. Unfortunately, traditional retiming algorithms pay no regard to maintaining the initial state. While some work has been carried out on finding a retiming of a circuit with equivalent initial states, it has concentrated on achieving a specified clock period without regard to the number of flip-flops. However, if the number of flip-flops is not explicitly minimized the retimed circuit may have a very large number of flip-flops. This work targets the problem of minimizing the number of flip-flops in control logic subject to a specified clock period and with a guarantee of an equivalent initial state. The problem is formulated as a mixed-integer linear program and bounds on the retiming variables are used to guarantee an equivalent initial state. These bounds also lead to a simple method for calculating an equivalent initial state for the retimed circuit. The mixed-integer linear program formulation is capable of modeling the maximum sharing of different types of flip-flops at the fanout of a gate. Experimental results on circuits of up to 9000 gates and are shown to be close to a (perhaps unachievable) lower bound. (C) 1999 Elsevier Science B.V. All rights reserved.

关键词： computer-aided design initial state integer linear programming retiming sequential circuits timing optimization VLSI

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A simulated annealing code for general integer linear programs

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ANNALS OF OPERATIONS RESEARCH 1999年第86期86卷 3-21页

作者： Abramson, D Randall, M Monash Univ Sch Comp Sci & Software Engn Dept Digital Syst Clayton Vic 3168 Australia

This paper explores the use of simulated annealing (SA) for solving arbitrary combinatorial optimisation problems. It reviews an existing code called GPSIMAN for solving 0-1 problems, and evaluates it against a commercial branch-and-bound code, OSL. The problems tested include travelling salesman, graph colouring, bin packing, quadratic assignment and generalised assignment. The paper then describes a technique for representing these problems using arbitrary integer variables, and shows how a general simulated annealing algorithm can also be applied. This new code, INTSA, outperforms GPSIMAN and OSL on almost all of the problems tested.

关键词： simulated annealing combinatorial optimisation integer linear programming

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Results of an experimental investigation of the efficiency of the global-equilibrium-search method

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CYBERNETICS AND SYSTEMS ANALYSIS 1999年第2期35卷 253-261页

作者： Shilo, VP

An adaptive random search method is proposed and studied in[1]forsolving problems of integer global optimization. This method has beencalled the global equilibrium search(GES). It was described asapplied to the problems of integer linear programming with Booleanvariables(ELP BV). The GES method conceptually relates to thesimulated-annealing method[2]and not only incorporates all of itsadvantages but also has a higher asymptotic efficiency. Results ofnumerical experiments with the use of the global-equilibrium-searchmethod and several well-known methods[3], which, from our point ofview, demonstrate the high computing efficiency of the GES method,are presented below.

关键词： Search methods REM1 gene Best value Random search method integer linear programming

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An ILP formulation for minimizing the number of feedthrough cells in a standard cell placement

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VLSI DESIGN 1999年第2期10卷 169-176页

作者： Yan, JT Natl Chiao Tung Univ Comp Syst Res Ctr Hsinchu Taiwan

It is well known that standard cells have been widely used to implement VLSI circuits in the automation of physical design. Since one major aim of a cell-based design is to minimize total layout area in a standard cell placement, the number of feedthrough cells will be minimized to reduce total cell area in a standard cell placement. In this paper, first, we model a partitioning-based row assignment (PRA) problem to minimize the number of feedthrough cells in a standard cell placement. Furthermore, an integer linear programming (ILP) approach is proposed to solve the PRA problem in a standard cell placement. Finally, the ILP approach has been implemented and two standard-cell net-lists, Primary 1 and Primary 2, have been tested by the proposed approach, Bose's approach [4] and an exhaustive search approach,respectively The experimental results show that the ILP approach obtains fewer feedthrough cells than Bose's approach in a partitioning-based standard cell placement.

关键词： physical design placement standard cell feedthrough cell integer linear programming

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