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检索条件"主题词=integer linear programming"

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Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs

Temporal partitioning combined with design space exploration...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： M. Kaul R. Vemuri Laboratory for Digital Design Environments Department of ECECS University of Cincinnati Cincinnati OH

We present combined temporal partitioning and design space exploration techniques for synthesizing behavioral specifications for run-time reconfigurable processors. Design space exploration involves selecting a design point for each task from a set of design points for that task to achieve latency minimization of partitioned solutions. We present an iterative search procedure that uses a core ILP (integer linear programming) technique, to obtain constraint satisfying solutions. The search procedure explores different regions of the design space while accomplishing combined partitioning and design space exploration. A case study of the DCT (discrete cosine transform) demonstrates the effectiveness of our approach.

关键词： Space exploration Delay Minimization Runtime environment Read only memory linear programming Discrete cosine transforms Circuits Contracts integer linear programming

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Test pattern generation for width compression in BIST

Test pattern generation for width compression in BIST

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： P. Flores H. Neto K. Chakrabarty J. Marques-Silva IST/INESC Technical University Lisboa Portugal Electrical and Computer Eng. Duke University USA IST/INESC Cadence European Laboratories Italy

The main objectives of built-in self test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test vectors and utilize the minimum circuit area. This paper targets the problem of generating test patterns for stuck-at faults that induce compatibility relations between the primary inputs of the circuit under test. These compatibility relations can be used for designing counter-based test generator circuits with a reduced number of bits, thus requiring smaller testing time and smaller area. The proposed solution is based on an integer linear programming (ILP) formulation that builds on existing propositional satisfiability (SAT) models for test pattern generation. An ATPG tool for minimum test pattern generation for width compression (MTP-C) is described, which illustrates the practical applicability of our approach for a wide range of benchmark circuits.

关键词： Test pattern generators Built-in self-test Circuit testing Circuit faults Automatic test pattern generation System testing Automatic testing Read only memory Counting circuits integer linear programming

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A lower bound on general minimal resource interval scheduling with arbitrary component selection

A lower bound on general minimal resource interval schedulin...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Z.X. Shen C.C. Jong Institute of High Performance Computing National University Singapore School of Electrical and Electronic Engineering Nanyang Technological University Singapore

Exploring lower bound of scheduling is an important problem in high-level synthesis, In this paper, we address the problem of computing lower bound on the general minimal resource interval scheduling problem, called n-n-MRIS, in which arbitrary component selections are allowed in stead of the traditional unicomponent selection. The problem of n-n-MRIS is proved to be strongly NP hard. An efficient ILP model and a surrogate relaxation technique are proposed to produce a lower bound for the n-n-MRIS problem.

关键词： Processor scheduling Magnetic resonance imaging High level synthesis Costs High performance computing Algorithm design and analysis Space exploration Hardware Performance loss integer linear programming

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A graph based framework to detect optimal memory layouts for improving data locality

A graph based framework to detect optimal memory layouts for...

引用

International Symposium on Parallel Processing

作者： M. Kandemir A. Choudhary J. Ramanujam P. Banerjee CPDC Department of Electrical and Computer Engineering Northwestern University Evanston IL USA Department of Electrical and Computer Engineering Louisiana State University Baton Rouge LA USA

In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advances in caches help in better utilization of the memory hierarchy, compiler-directed locality enhancement techniques are also important. In this paper we propose a locality improvement technique that uses data space (array layout) transformations in contrast to most of the previous work based on iteration space (loop) transformations. In other words, rather than changing the order of loop iterations, our technique modifies the memory layouts of multi-dimensional arrays. In comparison with previous work on data transformations it brings two novelties. First, we formulate the problem on a special graph structure called the layout graph (LG) and use integer linear programming (ILP) methods to determine optimal layouts. Second, in addition to static layout detection, our approach also enables the compiler to determine optimal dynamic layouts; that is, the layouts that can be changed across loop nest boundaries. We believe that this is the first attempt to determine optimal dynamic memory layouts. We also present preliminary experimental results on the SGI Origin 2000 distributed shared memory multiprocessor. Our results so far are encouraging and indicate that the additional compilation time taken by the solver is tolerable.

关键词： Random access memory Data structures Data mining Memory management integer linear programming Parallel machines Cache memory Optimizing compilers Program processors Law

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A technology-independent methodology of placement generation for analog circuit

A technology-independent methodology of placement generation...

引用

Asia and South Pacific Design Automation Conference

作者： Wai-Chee Wong P.C.H. Chan Wai-On Law Hong Kong University of Science and Technology Hong Kong China Motorola Semiconductors Hong Kong Limited

ISBN: (纸本)078035012X

An automatic placement system with emphasis on technology independent methodology and device matching consideration for analog layout design is presented. A novel optimization approach based on circuit partitioning, simulated annealing and a branch-and-bound algorithm is proposed to solve the placement problem. The move set used to generate perturbations for annealing is capable of arriving at any topological placement. The branch-and-bound is modified to take circuit performance into consideration. Results of two silicon proven designs generated by the system demonstrate an 8X cycle time reduction as compared to a manual approach.

关键词： Analog circuits Circuit simulation Simulated annealing Circuit optimization Routing Degradation Partitioning algorithms Silicon Costs integer linear programming

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Multi-criteria capital budgeting using FLIP

Multi-criteria capital budgeting using FLIP

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International Conference on Computational Intelligence and Multimedia Applications

作者： C. Kahraman Z. Ulukan Department of Industrial Engineering Istanbul Technical University Istanbul Turkey Faculty of Engineering and Technology Galatasaray University Istanbul Turkey

By using fuzzy linear programming (FLIP), tolerance intervals are used for calculating the availability of capital at each point in time. The main advantage, compared to the non-fuzzy problem formulation, is the fact that the decision maker is not forced into a precise formulation for mathematical reasons. linear membership functions which monotonically increase or decrease in the tolerance interval are used because they can be handled quite easily. A numeric example is given.

关键词： Proposals linear programming Electrical capacitance tomography Investments Uncertainty Water pollution Industrial engineering HTML Postal services integer linear programming

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Exploiting test resource optimization in data path synthesis for BIST

Exploiting test resource optimization in data path synthesis...

引用

Great Lakes Symposium on VLSI

作者： Xiaowei Li P.Y.S. Cheung Department of Computer Science and Technology Peking University Beijing China Department of Electrical and Electronic Engineering University of Hong Kong Hong Kong China

ISBN: (纸本)0769501044

Area and test time are two major overheads encountered during data path synthesis for BIST. This paper presents an attempt towards testability enhancement in data path BIST synthesis by considering two factors simultaneously. It is achieved by incorporating two testability constraints in data path synthesis. Experimental results are presented to demonstrate the effectiveness of the proposed (data path) BIST synthesis approach.

关键词： Built-in self-test Logic testing Costs Concurrent computing Computer science Test pattern generators Performance evaluation System testing integer linear programming Benchmark testing

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Tighter timing predictions by automatic detection and exploitation of value-dependent constraints

Tighter timing predictions by automatic detection and exploi...

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Real-Time Technology and Applications Symposium

作者： C. Healy D. Whaley Computer Science Department Florida State University Tallahassee FL USA

Predicting the worst case execution time (WCET) of a real time program is a challenging task. Though much progress has been made in obtaining tighter timing predictions by using techniques that model the architectural features of a machine, significant overestimations of WCET can still occur. Even with perfect architectural modeling, dependencies on data values can constrain the outcome of conditional branches and the corresponding set of paths that can be taken in a program. While value-dependent constraint information has been used in the past by some timing analyzers, it has typically been specified manually, which is both tedious and error prone. The paper describes efficient techniques for automatically detecting value-dependent constraints by a compiler and automatically exploiting these constraints within a timing analyzer. The result is tighter timing analysis predictions without requiring additional interaction with a user.

关键词： Timing Information analysis Performance analysis Computer science Electronic switching systems Predictive models Pipelines integer linear programming Automatic control Flow graphs

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On ILP formulations for built-in self-testable data path synthesis

On ILP formulations for built-in self-testable data path syn...

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Design Automation Conference

作者： Han Bin Kim Dong Sam Ha T. Takahashi Department of Electr. & Comput. Engineering Virginia Polytechnic Institute and State University Blacksburg VA USA Advantest Laboratories Limited Sendai Miyagi Japan

ISBN: (纸本)1581130929

In this paper, we present a new method for the built-in self-testable data path synthesis based on integer linear programming (ILP). Our method performs system register assignment, built-in self-test (BIST) register assignment, and interconnection assignment concurrently to yield optimal designs. Our experimental results show that our method successfully synthesizes BIST circuits for all six circuits experimented on. All the BIST circuits are better in area overhead than those generated by existing high-level BIST synthesis methods.

关键词： Built-in self-test Circuit testing Circuit synthesis Registers Integrated circuit interconnections High level synthesis integer linear programming Permission Scheduling Automatic testing

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An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications

An automated temporal partitioning and loop fission approach...

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Design Automation Conference

作者： M. Kaul R. Vemuri S. Govindarajan I. Ouaiss Digital Design Environments Laboratory University of Cincinnati Cincinnati OH USA

We present an automated temporal partitioning and loop transformation approach for developing dynamically reconfigurable designs starting from behavior level specifications. An integer linear programming (ILP) model is formulated to achieve near-optimal latency designs. We, also present a loop restructuring method to achieve maximum throughput for a class of DSP applications. This restructuring transformation is performed on the temporally partitioned behavior and results in near-optimization of throughput. We discuss efficient memory mapping and address generation techniques for the synthesis of reconfigurable designs. A case study on the Joint Photographic Experts Group (JPEG) image compression algorithm demonstrates the effectiveness of our approach.

关键词： Field programmable gate arrays Throughput Digital signal processing Delay Partitioning algorithms Image segmentation Hardware Permission integer linear programming Random access memory

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