In this paper we consider the determination of allocation functions as a part of the design of massively parallel processor arrays for algorithms which can be represented as systems of uniform recurrence equations. Th...
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In this paper we consider the determination of allocation functions as a part of the design of massively parallel processor arrays for algorithms which can be represented as systems of uniform recurrence equations. The objective is to find allocation functions minimizing the necessary chip area for a hardware implementation of the processor array. We propose an algorithm approximately minimizing the number of processors under consideration of the necessary chip area needed to implement the processors of the processor array. The arising optimization problems can be solved using integer linear programming.
Design of a real-time embedded control system is a complicated task, and an experienced designer is the best expert to control the system-level design. The interactive codesign approach presented in this paper provide...
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Design of a real-time embedded control system is a complicated task, and an experienced designer is the best expert to control the system-level design. The interactive codesign approach presented in this paper provides the designer with support for the functional specification and system partitioning phases. While adopting existing SA/VHDL specification and TripleS state reachability analysis methods and toolsets as front-end, a new method for supporting interactive system-level partitioning under various resource and performance constraints is proposed. The partitioning uses a zero-one integer linear programming model. Experiments with a CAN controller example show that the designer controlled partitioning provides detailed information for the system implementation design.
Branch-and-bound algorithm is applied to the design of sparse FIR filters having intentionally zeroed tap positions. It is shown that this algorithm coupled with a suitable optimization technique for filter design can...
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Branch-and-bound algorithm is applied to the design of sparse FIR filters having intentionally zeroed tap positions. It is shown that this algorithm coupled with a suitable optimization technique for filter design can lead to an optimal sparse FIR filter satisfying given specifications. Design examples demonstrate that the proposed method requires less computation than the conventional optimization such as the subset selection method.
Presents a timing graph technique for the optimization of multiple-phase edge-clocked circuits. By using this method, the timing of these synchronous systems can be analyzed and designed accurately, taking into accoun...
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Presents a timing graph technique for the optimization of multiple-phase edge-clocked circuits. By using this method, the timing of these synchronous systems can be analyzed and designed accurately, taking into account the corresponding temporal parameters involved. An optimization algorithm, which includes the effects of the setup and hold time and the propagation delays of the registers, is introduced. The optimal phase distribution is obtained by means of an integerlinear program. An iterative procedure for constraining the maximum number of phases is also proposed.
The channel assignment problem in a mobile cellular network is considered in this paper. The cellular network is most often modelled as a graph and the channel assignment problem is formulated as the coloring problem ...
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The channel assignment problem in a mobile cellular network is considered in this paper. The cellular network is most often modelled as a graph and the channel assignment problem is formulated as the coloring problem of that graph. The channel assignment problem in its most general form is NP-complete. Prior studies assume that the graph modelling the cellular network is an arbitrary graph. However, we show that the graph modelling the cellular network has a very regular structure and exploiting this regular structure, the channel assignment problem can be solved optimally in many cases. We also present an integer linear programming formulation of the channel assignment problem.
For a parallelizing compiler, mainly based on loop transformations, dependence information that is as complete and precise as possible is required. In this paper, we propose a generalized method for computing, in any ...
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For a parallelizing compiler, mainly based on loop transformations, dependence information that is as complete and precise as possible is required. In this paper, we propose a generalized method for computing, in any multi-dimensional loop, information which proved to be useful in the case of irregular dependences. Firstly, we solve the basic problem of the existence of a dependence with an algorithm composed of a preprocessing phase of reduction and of an integer simplex resolution. If a solution exists, we compute by integer simplex the bounds of the distances associated with loop indices. Depending on the values of these bounds, we finally define problems consisting in evaluating the bounds of slopes of dependence vectors, which we solve by integerlinear fractional programming. The amount of computation for each new problem is very low. This algorithm has been implemented as an extension of the Janus Test, which was presented in a previous work.
Edge-Valued Binary-Decision Diagrams (EVBDD's) are directed acyclic graphs that can represent and manipulate integer functions as effectively as Ordered Binary-Decision Diagrams (OBDD's) do for Boolean functio...
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Edge-Valued Binary-Decision Diagrams (EVBDD's) are directed acyclic graphs that can represent and manipulate integer functions as effectively as Ordered Binary-Decision Diagrams (OBDD's) do for Boolean functions. They have been used in logic verification for showing the equivalence between Boolean functions and arithmetic functions. In this paper, we present EVBDD-based algorithms for solving integerlinear programs, computing spectral coefficients of Boolean functions, and performing function decomposition. These algorithms have been implemented in C under the SIS environment and experimental results are provided.
We study a class of all-optical networks using wavelength-division multiplexing (WDM) and wavelength routing, in which a connection between a pair of nodes in the network is assigned a path and a wavelength on that pa...
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We study a class of all-optical networks using wavelength-division multiplexing (WDM) and wavelength routing, in which a connection between a pair of nodes in the network is assigned a path and a wavelength on that path, Moreover, on the links of that path no other connection can share the assigned wavelength, Using a generalized reduced load approximation scheme we calculate the blocking probabilities for the optical network model for two routing schemes: fixed routing and least loaded routing.
The rapid advances in high-performance computer architecture and compilation techniques provide both challenges and opportunities to exploit the rich solution space of software pipelined loop schedules. In this paper,...
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The rapid advances in high-performance computer architecture and compilation techniques provide both challenges and opportunities to exploit the rich solution space of software pipelined loop schedules. In this paper, we develop a framework to construct a software pipelined loop schedule which runs on the given architecture (with a fixed number of processor resources) at the maximum possible iteration rate (a la rate-optimal) while minimizing the number of buffers-a close approximation to minimizing the number of registers. The main contributions of this paper are: First, we demonstrate that such problem can be described by a simple mathematical formulation with precise optimization objectives under a periodic linear scheduling framework. The mathematical formulation provides a clear picture which permits one to visualize the overall solution space (for rate-optimal schedules) under different sets of constraints. Secondly, we show that a precise mathematical formulation and its solution does make a significant performance difference. We evaluated the performance of our method against three leading contemporary heuristic methods. Experimental results show that the method described in this paper performed significantly better than these methods. The techniques proposed in this paper are useful in two different ways: 1) As a compiler option which can be used in generating faster schedules for performance-critical loops (if the interested users are willing to trade the cost of longer compile time with faster runtime). 2) As a framework for compiler writers to evaluate and improve other heuristics-based approaches by providing quantitative information as to where and how much their heuristic methods could be further improved.
This paper presents a new simulated annealing approach to the solution of an integer linear programming formulation of the one-dimensional cutting stock problem. Design and implementation issues are discussed - includ...
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This paper presents a new simulated annealing approach to the solution of an integer linear programming formulation of the one-dimensional cutting stock problem. Design and implementation issues are discussed - including a thorough statistical analysis of the effects of various parameters on the efficiency and accuracy of solutions. The performance of the new algorithm is compared to that obtained using an existing simulated annealing based methodology, and results presented herein indicate that the new approach consistently generates more efficient solutions with respect to objective value and execution time.
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