This paper describes an exact symbolic formulation of control-dependent, resource-constrained scheduling. The technique provides a closed-form solution set in which all satisfying schedules are encapsulated in a compr...
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This paper describes an exact symbolic formulation of control-dependent, resource-constrained scheduling. The technique provides a closed-form solution set in which all satisfying schedules are encapsulated in a compressed OBDD-based representation. This solution format greatly increases the flexibility of the synthesis task by enabling incremental incorporation of additional constraints and by supporting solution space exploration without the need for rescheduling. The technique provides a systematic treatment of speculative operation execution in arbitrary forward-branching control/data paths. An iterative construction method is presented along with benchmark results. The experiments demonstrate the ability of the proposed technique to efficiently exploit parallelism not explicitly specified in the input description.
In this paper, we analyze some properties of the discrete linear bilevel program for different discretizations of the set of variables. We study the geometry of the feasible set and discuss the existence of an optimal...
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In this paper, we analyze some properties of the discrete linear bilevel program for different discretizations of the set of variables. We study the geometry of the feasible set and discuss the existence of an optimal solution. We also establish equivalences between different classes of discrete linear bilevel programs and particular linear multilevel programming problems. These equivalences are based on concave penalty functions and can be used to design penalty function methods for the solution of discrete linear bilevel programs.
Many regular algorithms, suitable for VLSI implementation, are naturally described by sets of integer index vectors together with a rule that assigns a computation to each vector. Regular VLSI structures for such algo...
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Many regular algorithms, suitable for VLSI implementation, are naturally described by sets of integer index vectors together with a rule that assigns a computation to each vector. Regular VLSI structures for such algorithms can be found by mapping the index vectors to a discrete space-time with integer coordinates. If the scope is restricted to linear or affine mappings, then the minimization of the execution time for the VLSI implementation with respect to the space-time mapping is essentially an integer linear programming (ILP) problem. If the entries in the vector describing the time function must be integers, ILP techniques can be applied directly. There are, however, index sets that allow space-time mappings with rational, nonintegral entries. In such cases, ILP will not consider all possible affine time functions and an optimal solution may go unnoticed. In this paper we give sufficient conditions on the index set for when only integer time functions are allowed. We also give a general algorithm to find a ''preconditioning'' affine transformation of the index set, such that the transformed index set allows only integer time functions. ILP methods can then be used to find time-optimal architectures for the transformed algorithm. This considerably extends the class of algorithms for which time-optimal VLSI structures can be found.
Previous results have shown that the class of quasi-cyclic (QC) codes contains many good codes. In this paper, new rate (m-1)/pm QC codes over GF(3) and GF(4) are presented. These codes have been constructed using int...
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Previous results have shown that the class of quasi-cyclic (QC) codes contains many good codes. In this paper, new rate (m-1)/pm QC codes over GF(3) and GF(4) are presented. These codes have been constructed using integer linear programming and a heuristic combinatorial optimization algorithm based on a greedy local search. Most of these codes attain the maximum possible minimum distance for any linear code with the same parameters, i.e., they are optimal, and 58 improve the maximum known distances. The generator polynomials for these 58 codes are tabulated, and the minimum distances of rate (m-1)/pm QC codes are given.
In this paper, a distinction is drawn between research which assesses the suitability of the Hopfield network for solving the traveling salesman problem (TSP) and research which attempts to determine the effectiveness...
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In this paper, a distinction is drawn between research which assesses the suitability of the Hopfield network for solving the traveling salesman problem (TSP) and research which attempts to determine the effectiveness of the Hopfield network as an optimization technique. It is argued that the TSP is generally misused as a benchmark for the latter goal, with the existence of an alternative linear formulation giving rise to unreasonable comparisons.
In Colombia, power companies with capacity greater than 100 MW pay royalties over gross sales for rural electrification programs. These contributions are collected by regional development corporations (RDC) with a jur...
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Modular mappings have been recently proposed for optimization of algorithms that cannot be efficiently mapped by affine mappings. This paper addresses the problem of generating modular mappings that satisfy conditions...
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ISBN:
(纸本)081867542X
Modular mappings have been recently proposed for optimization of algorithms that cannot be efficiently mapped by affine mappings. This paper addresses the problem of generating modular mappings that satisfy conditions for validity and optimality. In general, this is a difficult problem due to the presence of non-linear constraints. Hence, a method of O(n/sup 2/) complexity is provided to assign values to some entries of a transformation matrix so that non-linear constraints are transformed into linear ones, where n is the dimension of a computation domain. The proposed heuristic attempts to reduce the number of value-assigned entries and exclude as few solutions as possible. This paper also considers the issue of deriving the inverse transformation of a given modular mapping. It identifies a class of modular functions whose inverses result directly from computing the inverse of the (coefficient) matrix used to specify a modular mapping. An efficient method of O(n/sup 2/) complexity is provided to formulate the problem of generating such modular mappings as an integer linear programming problem.
In the present paper, trim loss problems connected to the paper-converting industry are analyzed and solved. The objective is to produce a set of paper rolls from storage rolls such that a cost function including the ...
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In the present paper, trim loss problems connected to the paper-converting industry are analyzed and solved. The objective is to produce a set of paper rolls from storage rolls such that a cost function including the minimization of the trim loss as well as the time for cutting is considered. The problem is a non-convex integer non-linearprogramming (INLP) problem, due to its bilinear constraints. The problem can, however, be written in an expanded linear form and can, thus, be solved as an integer linear programming (ILP) or a mixed integer linear programming (MILP) problem. The linear formulation is attractive from the point of view of formality. One drawback of linear formulations is the increased number of variables and constraints they give rise to. It is, though, of interest to compare different ways of describing the problem as an ILP/MILP problem. There has previously been some academic interest in solving trim loss problems as linearprogramming problems. In this paper, we will present a general INLP formulation, some ways to formulate and solve it as an ILP or MILP problem and compare the efficiency of these different approaches. The examples considered are taken from real daily trim optimization problems encountered at a Finnish paper-converting mill with a capacity of 100,000 tons/year.
We relax an integerlinear vector optimization problem [[Pbar]]. whose vector of variables ia additionally bounded from above. neglecting the upper and lowcr bounds of the basic variables. The relaxation is transforme...
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We relax an integerlinear vector optimization problem [[Pbar]]. whose vector of variables ia additionally bounded from above. neglecting the upper and lowcr bounds of the basic variables. The relaxation is transformed into an equivalent muliizriteria prcup knapsack problem and this into a shortest path problem on a vectorially valued graph. The efficient points of the relaxation can be calculated from the solutions ol the corresponding group knapsack or shortesr path problem respectively. We derive a sufficient condition for the fact that the efficiency set of the relaxation contains elements feasible and thus efficient for problem [[Pbar]] Besides. criteria for finding the complete solution of the integerlinear vector optimization problem by solving the relaxation are developed.
We present a novel approach to synthesizing hardware implementation from hardware description language (HDL) programs that could not be automatically synthesized before. We deal with multi phase/multi stage designs, a...
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We present a novel approach to synthesizing hardware implementation from hardware description language (HDL) programs that could not be automatically synthesized before. We deal with multi phase/multi stage designs, and demonstrate that this problem can be mapped into a class of timed automata which is called "multi phase" finite state machines (FSM). We propose three procedures to decompose a multi phase FSM into a network of interacting single phase FSMs. The first two procedures are based on the region graph expansion of a timed automata (R. Alur and D. Dill, 1990). The first procedure extracts single phase FSMs iteratively from a region graph. The second procedure formulates the decomposition problem as an integer linear programming. These two region graph based procedures may suffer from explosion in the number of regions. The third procedure, without building intermediate transition structures, constructs single phase FSMs directly from the transition structure of a multi phase FSM. It is more efficient but redundancy might exist in the constructed FSMs. Not only can these procedures be used for the synthesis from a multi phase design, they can also be used to speed up FSM based simulation.
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