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A CELL-BASED HIERARCHICAL PITCHMATCHING COMPACTION USING MINIMAL LP

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1995年第4期14卷 523-526页

作者： YAO, SZ CHENG, CK DUTT, D NAHAR, S LO, CY UNIV CALIF SAN DIEGO DEPT COMP SCI & ENGNLA JOLLACA 92093 AT&T BELL LABS ALLENTOWNPA 18103 AT&T BELL LABS MURRAY HILLNJ 07974

We describe a new linear programming (LP)-based hierarchical pitchmatching method. With a simplified treatment of the intercell constraints, the size of the LP problems is significantly reduced as compared to the best known results. In particular, the pitchmatching problem is decomposed into independent subproblems bg exploiting the layout slicing structure. Each subproblem is further ''folded'' to reduce the LP problem size, We prove that the new method generates smaller LP problem than the previously best known approach. Experimental data show that the LP problem size can be 10 times smaller.

关键词： Compaction Design automation linear programming Explosions Databases Timing integer linear programming NP-complete problem Circuits Computational efficiency

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The NC equivalence of planar integer linear programming and Euclidean GCD

The NC equivalence of planar integer linear programming and ...

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Annual IEEE Symposium on Foundations of Computer Science

作者： D. Shallcross V. Pan Yu Lin-Kriz Bellcore Morristown NJ USA International Computer Science Institute Berkeley CA USA Department of Mathematics and Computer Science Lehman College of the City University of New York Bronx NY USA Graduate Center of the City University of New York NY USA

We show NC-reduction of integer linear programming with two variables to the evaluation of the remainder sequence arising in the application of the Euclidean algorithm to two positive integers. Due to the previous result of X. Deng (1989), this implies NC-equivalence of both of these problems, whose membership in NC, as well as P-completeness, remain unresolved open problems.< >

关键词： integer linear programming Computer science Polynomials Computational complexity Concurrent computing Mathematics Educational institutions Cities and towns Equations Lattices

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A parallel branch‐and‐bound algorithm for integer linear programming and its implementation on a distributed multiprocessor

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Systems and Computers in Japan 1993年第3期24卷 35-47页

作者： Ikegami, Atsuko Aoyagi, Katsuhiro Iizuka, Hajime Faculty of Engineering Seikei University Tokyo 180 Japan Electronics Research Laboratories Nippon Steel Corporation Kanagawa 229 Japan

This paper describes a parallel branch‐and‐bound algorithm for general integer linear programming problems and its implementation on a distributed memory multiprocessor nCUBE2. With a branch‐and‐bound algorithm, the amount of computation on each search tree node varies, and in general, is large. This has led to development of an effective communication strategy for the algorithm presented herein. Its implementation and performance evaluation also are described. The results show that the more difficult the problem instances become in terms of time to solve on a sequential computer, the more efficient the algorithm presented here proves to be. Copyright © 1993 Wiley Periodicals, Inc., A Wiley Company

关键词： branch‐and‐bound algorithm integer linear programming nCUBE2 distributed memory multiprocessor Parallel processing

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Register minimization in cost-optimal synthesis of DSP architectures

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Workshop on VLSI Signal Processing

作者： R. Ito K.K. Parhi Department of Electrical and Electrical System Engineering Saitama University Urawa Saitama Japan Department of Electrical Engineering University of Minnesota Minneapolis MN USA

In this paper we propose a generalized technique to count the number of registers supporting overlapped scheduling and a general digit-serial data format. This technique is integrated into an integer linear programming model which minimizes the cost of registers as well as the cost of processors and data format converters to synthesize a cost-optimal architecture for a given digital signal processing algorithm. It is shown that by including the cost of registers in the synthesis task as proposed in this paper leads to up to 12.8% savings in the total cost of the synthesized architecture when compared with synthesis performed without including the register cost in the total cost.

关键词： Digital signal processing Processor scheduling Registers Costs Signal synthesis Signal processing algorithms integer linear programming High level synthesis Process design Delay

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Solving mathematical programming problems with OWA operators as objective functions

Solving mathematical programming problems with OWA operators...

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IEEE International Conference on Fuzzy Systems (FUZZ-IEEE)

作者： R.R. Yager Machine Intelligence Institute Iona College New Rochelle NY USA

The ordered weighted averaging (OWA) operators are introduced and some of their properties described. Attention is then focused on the problem of maximizing an objective function which is of the form of an OWA aggregation of a group of variables that are interrelated and constrained by a collection of linear inequalities. It is shown how this problem can be modeled as a integer linear programming problem. Use is made of this procedure to provide a solution to fuzzy linear programming problems in which some linguistically proscribed number of the goals must be satisfied.< >

关键词： Mathematical programming Open wireless architecture linear programming Machine intelligence Educational institutions integer linear programming Aggregates

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DSP synthesis with heterogeneous functional units using the MARS-II system

DSP synthesis with heterogeneous functional units using the ...

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Asilomar Conference on Signals, Systems & Computers

作者： Yun-Nan Chang Ching-Yi Wang K.K. Parhi Department of Electrical Engineering University of Minnesota Minneapolis MN USA

This paper presents a new heuristic, concurrent, iterative loop based scheduling and allocation algorithm for high-level synthesis of digital signal processing (DSP) architectures using heterogeneous functional units. In a heterogeneous architecture, functional units could be either bit-serial or digit-serial or bit-parallel. This paper assumes a library of heterogeneous implementation style based functional units to be available. The proposed heuristic synthesis approach generates optimal and near-optimal area solutions. Although optimum synthesis of such architectures were proposed using an integer linear programming (ILP) model our method can produce similar solutions in one to two orders of magnitude less time, at the expense of sacrificing the cost optimality. This new approach has been incorporated into the Minnesota Architecture Synthesis (MARS-II) system.

关键词： Digital signal processing High level synthesis Hardware Signal synthesis integer linear programming Cost function Real time systems Solid state circuit design Clocks Software libraries

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Lagrangian techniques for solving a class of zero-one integer linear programs

Lagrangian techniques for solving a class of zero-one intege...

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IEEE Annual International Computer Software and Applications Conference (COMPSAC)

作者： Y.-J. Chang B.W. Wah Coordinated Science Laboratory University of Illinois Urbana IL USA

We consider a class of zero-one integer programming feasibility problems (0-1 ILPF problems) in which the coefficients of variables can be integers, and the objective is to find an assignment of binary variables so that all constraints are satisfied. We propose a Lagrangian formulation in the continuous space and develop a gradient search in this space. By using two counteracting forces, one performing gradient search in the primal space (of the original variables) and the other in the dual space (of the Lagrangian variables), we show that our search algorithm does not get trapped in local minima and reaches equilibrium only when a feasible assignment to the original problem is found. We present experimental results comparing our method with backtracking and local search (based on random restarts). Our results show that 0-1 ILPF problems of reasonable sizes can be solved by an order of magnitude faster than existing methods.

关键词： Lagrangian functions integer linear programming Search methods Computer applications Application software Simulated annealing Genetic algorithms Minimization methods Equations

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Scheduling for optimum data memory compaction in block diagram oriented software synthesis

Scheduling for optimum data memory compaction in block diagr...

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： S. Ritz M. Willems H. Meyr RWTH Aachen University of Technology Aachen Germany Rheinisch-Westfalische Technische Hochschule Aachen Aachen Nordrhein-Westfalen DE Tech. Hochschule Aachen Germany

For the design of complex digital signal processing systems, block diagram oriented synthesis of real time software for programmable target processors has become an important design aid. The synthesis approach discussed in the paper is based on multirate block diagrams with scalable synchronous dataflow (SSDF) semantics. For this class of dataflow graphs the authors present scheduling techniques for optimum data memory compaction. These techniques can be employed to map signals of a block diagram onto a minimum data memory space. In order to formalize the data memory compaction problem, they first derive appropriate implementation measures. Based on these implementation measures it can be shown that optimum data memory compaction consists of optimum scheduling as well as optimum memory allocation. For the class of single appearance (SA) block diagrams with SSDF semantics, scheduling can be reduced to an integer linear programming (ILP) problem. Due to the computational complexity of ILP, the authors also present a suboptimum scheduling selection criterion, which call be used for SA and non SA-schedulers.

关键词： Compaction Processor scheduling Signal design Signal synthesis Digital signal processing Real time systems integer linear programming Computational complexity

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Computing approximate blocking probabilities for a class of all-optical networks

Computing approximate blocking probabilities for a class of ...

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IEEE Annual Joint Conference: INFOCOM, IEEE Computer and Communications Societies

作者： A. Birman T.J. Watson Research Center IBM Yorktown Heights NY USA

Studies a class of all-optical networks using wavelength division multiplexing and wavelength routing in which a connection between a pair of nodes in the network is assigned a path and a wavelength on that path. Moreover, on the links of that path no other connection can share the assigned wavelength. Using a generalized reduced load approximation scheme the authors calculate the blocking probabilities for the optical network model for two routing schemes: fixed routing and least loaded routing.

关键词： Computer networks All-optical networks Wavelength routing Switching circuits WDM networks Probability Optical fiber networks Heuristic algorithms Wavelength assignment integer linear programming

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Low power data format converter design using semi-static register allocation

Low power data format converter design using semi-static reg...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： K. Srivatsan C. Chakrabarti L. Lucke Department of Electrical Engineering Arizona State University Tempe AZ USA Department of Electrical Engineering University of Minnesota Minneapolis MN USA

In many applications, such as digital signal processing, data format converters are used to reformat the data transferred between processing modules. In VLSI implementations, these converters consume a large portion of the available resources. Various methods have been proposed to synthesize data format converter architectures while optimizing the number of registers used to store the data. In this paper, we present a new register allocation scheme which not only minimizes the number of resistors, but also minimizes the power consumption in the data format converter. Low power data format converters are synthesized by minimizing the transitions and interconnections between the registers used to store the data. We present both a heuristic and an integer linear programming formulation to solve the allocation problem. Our method shows significant improvement over previous techniques.

关键词： Registers Digital-to-frequency converters Energy consumption Integrated circuit interconnections Very large scale integration Circuit synthesis Signal processing Signal synthesis integer linear programming Matrix converters

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