A parallel testing graph (PTG) is offered to deal with the test scheduling problem; test scheduling in this paper refers to finding an optimal test generation scheme that allocates subcircuits or part of each subcircu...
详细信息
ISBN:
(纸本)0818649909
A parallel testing graph (PTG) is offered to deal with the test scheduling problem; test scheduling in this paper refers to finding an optimal test generation scheme that allocates subcircuits or part of each subcircuit to the processors in a multiprocessor system. Test generation of subcircuits that can be run simultaneously should not share the same multiplexer in the process of test generation. The test scheduling problem is reduced to the vertex coloring of the PTG; and then the test scheduling problem is found to be solvable in quadratic time. Certainly, the number of sequential test generation events is equal to the vertex chromatic number of the PTG. The problem is how to minimize the vertex chromatic number of the PTG. On the basis of these results, an integer linear programming model is offered to design for maximum parallelism of the test generation problem, which minimizes the vertex chromatic number of the PTG, and thereby, maximizes the parallelism of the problem.< >
We develop an exact algorithm for selecting flip-flops in partial scan designs to break all feedback cycles. The main ideas that allowus to solve this hard problemexactly for large, practical instances are - graph tra...
详细信息
ISBN:
(纸本)9780897916530
We develop an exact algorithm for selecting flip-flops in partial scan designs to break all feedback cycles. The main ideas that allowus to solve this hard problemexactly for large, practical instances are - graph transformations, a partitioning scheme used in the branch and bound procedure, and pruning techniques based on an integer linear programming formulation of the minimum feedback vertex set (MFVS) *** have obtained optimum solutions for the ISCAS '89 benchmark circuits and several production VLSI circuits within reasonable computation time. For example, the optimal number of scan flip-flops required to eliminate all cycles except self-loops in the circuit s38417 is 374. This optimal solution was obtained in 32 CPU seconds on a SUN Sparc 2 workstation.
This paper describes a new method for optimising the operation of stand-alone hybrid power systems containing some combination of auxiliary generator, PV generation and storage battery. The method provides a fast and ...
详细信息
This paper describes a new method for optimising the operation of stand-alone hybrid power systems containing some combination of auxiliary generator, PV generation and storage battery. The method provides a fast and accurate solution to the optimisation problem relative to previous methods. The method has been implemented on computer and an example control policy produced by the new method is presented and discussed. A comparison has been made between the new method and a conventional control algorithm under a simulation environment and using a deterministic future. This comparison has identified potential to reduce system operating costs.
A novel integer linear programming (ILP) formulation for optimally mapping a partitioned signal processing algorithm on a multiple FPGA board is presented. Our approach performs all the following synthesis bindings si...
详细信息
A novel integer linear programming (ILP) formulation for optimally mapping a partitioned signal processing algorithm on a multiple FPGA board is presented. Our approach performs all the following synthesis bindings simultaneously: operation scheduling, function unit allocation, interconnections, data-transfer scheduling between FPGAs, and input/output port allocation. Moreover, we present architectural models suitable for multiple FPGA boards and account for limitations in the structure of interconnections of multiple FPGAs. We demonstrate the quality of the results of our approach for typical signal processing synthesis benchmarks, including the difficult examples of discrete and inverse discrete cosine transforms (DCT and IDCT).< >
A method based on the 0-1 integer linear programming (ILP) model aiming primarily at minimizing the cost of interconnections is proposed for solving the data path allocation problem using multiport memories. The inter...
详细信息
A method based on the 0-1 integer linear programming (ILP) model aiming primarily at minimizing the cost of interconnections is proposed for solving the data path allocation problem using multiport memories. The interconnection elements are generally composed of buses, multiplexers, and tri-state buffers. After solving the operation binding problem, we first find the number of buses required. Then we deal with the multiport memory allocation problem simultaneously minimizing the cost of multiplexers and tri-state buffers. From the solution quality and execution time of the experimental results, we see that our method is suitable for solving data path allocation problem using multiport memories when the cost of interconnections is first considered.< >
At present, datapath synthesis techniques produce a design with a large number of isolated registers. Allocation of memory modules to implement these resisters are usually left to the designer. This paper presents new...
详细信息
At present, datapath synthesis techniques produce a design with a large number of isolated registers. Allocation of memory modules to implement these resisters are usually left to the designer. This paper presents new approach to the allocation of multiport memories which minimizes hardware costs in ASIC datapath synthesis. The proposed approach, AMD, considers not only the access requirements of registers but also the lifetime of registers. The objective is to minimize the requirement of registers and multiport memory modules under a given resource constraints simultaneously. The minimization problem has been modeled as a 0-1 integer linear programming problem. This approach is illustrated with an example.< >
Data flow languages are a natural way to describe the flow of computations in a DSP application. The SILAGE language has been developed for this purpose. It contains also more-dimensional arrays of signals and a natur...
详细信息
Data flow languages are a natural way to describe the flow of computations in a DSP application. The SILAGE language has been developed for this purpose. It contains also more-dimensional arrays of signals and a natural extension of it, delayed versions of arrays, e.g. to represent previous frames in video applications. The paper describes new data flow analysis techniques, to support multi-dimensional arrays. It checks single assignment of arrays, checks if for each consumption of an indexed signal, there is a production, and it will create data dependencies between productions and consumptions. These problems are formulated as integer linear programming problems. This formulation is independent of the number of signals in the arrays. Results show very fast running times (<1 s) for problems more than a hundred nodes.< >
The necessity for multiple hypothesis tracking (MHT) is recognized throughout the SDI tracking community. But, implementations of MHT techniques have required enormous amounts of computer time and memory. An efficient...
详细信息
The necessity for multiple hypothesis tracking (MHT) is recognized throughout the SDI tracking community. But, implementations of MHT techniques have required enormous amounts of computer time and memory. An efficient method of measurement-to-target association that makes MHT practical for the first time is presented. The method finds the exact N-best feasible hypotheses directly from a sequence of linear assignment problem solutions.
The problem of state reduction in a finite state machine (FSM) is important to reduce the complexity of a sequential circuit. In this paper, we present an efficient algorithm for state minimization in incompletely spe...
详细信息
The problem of state reduction in a finite state machine (FSM) is important to reduce the complexity of a sequential circuit. In this paper, we present an efficient algorithm for state minimization in incompletely specified state machines. This algorithm employs a tight lower bound and a fail-first heuristic, and generates a relatively small search space from the prime compatibles. It utilizes efficient pruning rules to further reduce the search space and finds a minimal closed cover. The technique guarantees the elimination of all the redundant states in a very short execution time. Experimental results with a large number of FSM's including the MCNC FSM benchmarks, are presented. The results are compared with other recent work in the area.
In this paper, a new technique is presented for the resource constrained scheduling problem in high level synthesis. This approach works by successively partitioning the control steps into zones and solving each of th...
详细信息
In this paper, a new technique is presented for the resource constrained scheduling problem in high level synthesis. This approach works by successively partitioning the control steps into zones and solving each of them by a 0-1 integer linear programming technique. By specifying the maximum number of 0-1 variables involved within a zone, the model can be turned into an optimal ILP scheduling, a list scheduling, or one in between with different speed/quality characteristics. Experiments show that better results than those achieved by list scheduling have been obtained with an acceptable computation overhead.
暂无评论