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Loading problems with tool management in flexible manufacturing systems: A few integer programming models

International Journal of Flexible Manufacturing Systems 1991年第1期3卷 71-82页

作者： de Werra, D. Widmer, M. Département de Mathématiques Chaire de Recherche Opérationnelle Ecole Polytechnique Fédérale de Lausanne Lausanne CH-1015 Switzerland Département de Mathématiques Chaire de Recherche Opérationnelle Ecole Polytechnique Fédérale de Lausanne Lausanne CH-1015 Switzerland

In automated production systems like flexible manufacturing systems (FMSs), an important issue is to find an adequate workload for each machine for each time period. Many integer linear programming (ILP) models have been proposed to solve the FMS loading problems, but not all of them take tools into account. Those that do not consider tooling are quite unrealistic, especially when setup times are important with respect to processing times. When tool loading has to be handled by the model, the load assignment may have to be changed completely. In this article we consider FMSs with a tool management of the following type: the system works in time periods whose durations are fixed or not;and tools are loaded on the machines at the beginning of each time period and stay there for the whole time period. Tool changes may occur only at the end of each time period when the system is stopped. We present some integer programming models for handling these situations with several types of objectives. Emphasis is laid on the ILP formulations. Computational complexities are discussed. © 1991 Kluwer Academic Publishers.

关键词： flexible manufacturing system integer linear programming loading problems modeling production tool management

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A FORMAL APPROACH TO THE SCHEDULING PROBLEM IN HIGH-LEVEL SYNTHESIS

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1991年第4期10卷 464-475页

作者： HWANG, CT LEE, JH HSU, YC Department of Computer Science Tsinghua University Hsinchu Taiwan

This paper presents an integer linear programming (ILP) model for the scheduling problem in high level synthesis. In addition to time-constrained scheduling and resource-constrained scheduling, a new scheduling problem called feasible scheduling is constructed, which provides a paradigm for exploring the solution space. Extensive consideration is given to the following applications: scheduling with;chaining;multicycle operations by nonpipelined function units;multicycle operations by pipelined function units;functional pipelining;loop folding;mutually exclusive operations;scheduling under bus constraint;minimizing lifetimes of variables. The complexity of the number of variables in the formulation is O (s . n) where s and n are the number of control steps and operations, respectively. Since we use the as soon as possible (ASAP), as late as possible (ALAP), and list scheduling techniques to reduce the solution space, the formulation becomes very efficient. A solution to a practical problem, such as the fifth-order filter, can be found optimally in a few seconds.

关键词： High level synthesis Digital systems Space exploration Scheduling algorithm Timing integer linear programming Pipeline processing Filters Hardware design languages Flow graphs

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A NEURAL NETWORK APPROACH TO JOB-SHOP SCHEDULING

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IEEE TRANSACTIONS ON NEURAL NETWORKS 1991年第1期2卷 175-179页

作者： ZHOU, DN CHERKASSKY, V BALDWIN, TR OLSON, DE UNIV MINNESOTA DEPT ELECT ENGNMINNEAPOLISMN 55455

This paper presents a novel analog computational network for solving NP-complete constraint satisfaction problems, i.e., job-shop scheduling. In contrast to most neural approaches to combinatorial optimization based on quadratic energy cost function, we propose to use linear cost functions. As a result, the network complexity (number of interconnections) grows only linearly with problem size, and large-scale implementations become possible. The proposed approach is related to the linear programming network described by Tank and Hopfield, which also uses a linear cost function for a simple optimization problem. In this paper we show how to map a difficult constraint satisfaction problem (job-shop scheduling) onto a simple neural net, where the number of neural processors equals the number of subjobs (operations), and the number of interconnections grows linearly with the total number of operations. Simulations show that our approach produces better solutions than existing neural approaches to job-shop scheduling, i.e. the TSP-type Hopfield approach and integer linear programming approach of Foo and Takefuji in terms of the quality of the solution and the network complexity, i.e., the number of neurons and the number of resistive interconnections.

关键词： Neural networks Processor scheduling Cost function Analog computers Computer networks Neurons Large-scale systems linear programming Traveling salesman problems integer linear programming

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CHANNEL DENSITY REDUCTION BY ROUTING OVER THE CELLS

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1991年第8期10卷 1067-1071页

作者： LIN, MS PERNG, HW HWANG, CY LIN, YL Department of Computer Science Tsinghua University Hsinchu Taiwan

We propose a new approach for reducing the density of a channel by routing some nets (or subnets) over the cells (i.e., outside the channel). Previous research assumed that the more nets being routed over the cells the greater the reduction in the channel density. We show that only the removal of critical nets contributes to the reduction in the channel density. We divide channel into zones where each zone has a zone density and the removal of any net from a zone will reduce its density by one. In order to reduce the channel density, only certain critical zones need to have their nets routed over the cells. A bipartite graph is used to represent the relationship between nets and zones. The problem is transformed into a constrained covering problem and formulated as an integer linear programming problem. In comparison with previous research, our approach reduces more channel densities while using fewer tracks over the cells. For Deutsch's difficult channel, a previous approach needs 15 tracks over the cells to reduce the channel density by 3 while we need only 5 tracks to achieve the same result.

关键词： OVER-THE-CELL ROUTING CHANNEL DENSITY REDUCTION STANDARD-CELL LAYOUT VLSI ROUTING integer linear programming

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Job scheduling on parallel machines using simulated annealing

Job scheduling on parallel machines using simulated annealin...

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IEEE International Conference on Systems, Man and Cybernetics

作者： Z.-P. Lo B. Bavarian Department of Electrical and Computer Engineering University of California Irvine Irvine CA USA

The authors consider the problem of scheduling a set of simultaneously available jobs on several parallel machines. Specifically, the minimization of the time to finish all the jobs assigned to all machines of scheduling sequence under job deadline constraints for the n jobs, m machines problem is formulated. The simulated annealing and fast simulated annealing algorithms are reviewed and adopted for the scheduling problem. A large number of simulations were carried out which provides an empirical basis for comparing the application of classical simulated annealing and fast simulated annealing algorithms to the scheduling problem.< >

关键词： Parallel machines Simulated annealing Processor scheduling Scheduling algorithm Differential equations Computational modeling Uninterruptible power systems Switches Timing integer linear programming

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An optimal design for parallel testing

An optimal design for parallel testing

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Pacific Rim International Symposium on Fault Tolerant Systems

作者： Xiang Dong Wei Daozheng Chen Tinghuai CAD Laboratory ICT Academia Sinica Beijing China Computer Department Chongqing University Chongqing China

ISBN: (纸本)081862275X

An integer linear programming (ILP) model is presented for the design of optimal parallel testing, which minimizes the index number of the maximal complete subgraph (MCS) in the parallel testing graph (PTG), therefore, making the index coloring number of the PTG minimal. The whole test time of a partitioned circuit is thus minimal. An optimal testing scheduling algorithm of a partitioned circuit is also presented in polynomial time. An existent ILP program is used to prove the correctness of this model. Sufficient experimental results corresponding to this ILP model are offered.< >

关键词： Circuit testing Circuit faults Costs System testing Parallel processing Processor scheduling Concurrent computing Design automation Laboratories integer linear programming

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Post-processor for data path synthesis using multiport memories

Post-processor for data path synthesis using multiport memor...

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IEEE International Conference on Computer-Aided Design

作者： I. Ahmad C.Y.R. Chen Department of Electrical and Computer Engineering Syracuse University Syracuse NY USA

A novel design methodology for data path synthesis using multiport memories is presented which can be applied to scheduled algorithms or to already synthesized data paths as a postprocessor to reduce the design space. Based on simple and clear but powerful principles, the proposed technique not only groups variables to a minimum number of multiport memories depending on their ports and taking into consideration the variables' access requirements, but also minimizes their interconnection hardware (such as buses, multiplexers, and tri-state buffers) to functional units. The system, MAP, supports the synthesis of architecture in both linear topology and random topology for the application-specific design. The minimization problems have been formulated as 0-1 integer linear programming problems. Experiments on benchmarks show very promising results and the CPU time for all the benchmarks is less than 1.4 s.< >

关键词： Registers Topology Multiplexing Design methodology Processor scheduling Scheduling algorithm Algorithm design and analysis Power system interconnection Hardware integer linear programming

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Neural network approach to zero-one optimal covering problem

Neural network approach to zero-one optimal covering problem

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Annual Symposium on Simulation

作者： A.R. Khan A.R. Marudarajan C.A. Goben Department of Electrical Engineering Southem Illinois University Carbondale IL USA

This paper reports the investigation of the neural network solution to the zero-one optimal covering problem via computer simulation. The key idea used in this exploration is that for every covering problem there exists an equivalent integer linear programming problem which can be solved by modifying the linear programming neural net circuit proposed by Tank and Hopfield. Simulation results indicate that this method works very well.< >

关键词： Neural networks Neurons Resource management Computer simulation Very large scale integration integer linear programming linear programming Hopfield neural networks Circuits Computational modeling

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A new integer linear programming formulation for the scheduling problem in data path synthesis

A new integer linear programming formulation for the schedul...

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IEEE International Conference on Computer-Aided Design

作者： Jiahn-Hung Lee Yu-Chin Hsu Youn-Long Lin Department Computer Science Tsinghua University Hsinchu Taiwan

A novel approach is presented to the operation scheduling problem in a data path synthesis. After obtaining the start time and the require time of each operation by the ASAP (as soon as possible) and ALAP (as late as possible) methods, respectively, an integer linear programming (ILP) formulation is formed to solve the scheduling problem. The objective is to fully utilize the hardware resources, i.e. to minimize the requirement of function units under a given timing constraint. The formulation can be generalized to support multicycle operations, multiple operations per cycle, pipelined data paths, mutually exclusive operations, and variables' lifetime consideration in a data path. A fifth-order filter containing 26 addition and 8 multiplication operations can be scheduled optimally for the cases from 17 cycles to 21 cycles per minute on a VAX-11/8800.< >

关键词： integer linear programming Processor scheduling Cost function Timing linear programming Computer science Hardware Filters Automatic control Councils

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An integrated layout system for sea-of-gates module generation

An integrated layout system for sea-of-gates module generati...

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European Conference on Design Automation

作者： P. Duchene M. Declercq S.M. Kang Federal Institute of Technology Electronics Laboratory Lausanne Switzerland Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA

Presents a sea-of-gates layout system able to design medium-size logic circuits in a true channelless fashion. The methodology relies on flexible leaf cell generation, systematic cell terminal abutment, a global routine scheme using integer linear programming methods, and a step-wise compaction-rerouting refinement. Modules up to several hundred transistors have been laid out compactly with more than 80% transistor utilization with two layers of metal. With top-down hierarchy, those modules can be used as macrocells.< >

关键词： Macrocell networks Routing Libraries Design methodology Consumer electronics Integrated circuit technology Logic circuits integer linear programming Application specific integrated circuits Modems

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