Computer aided synthesis of circuit structures from behavioural level specifications has become a standard procedure in the design of integrated circuits. One disadvantage of several existing synthesis systems is thei...
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Computer aided synthesis of circuit structures from behavioural level specifications has become a standard procedure in the design of integrated circuits. One disadvantage of several existing synthesis systems is their lack of efficiency with respect to chip area and processing speed. Within this paper several optimizations on different levels in the synthesis process are described. It is distinguished between datapath and control part as well as between pure minimizations and optimization trade-offs.
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