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Characterization of real time iterative array by alternating device

THEORETICAL COMPUTER SCIENCE 2003年第3期290卷 2075-2084页

作者： Terrier, V Univ Caen Dept Informat GREYC F-14032 Caen France

In this paper, we show that real time k-dimensional iterative arrays are equivalent through reverse to real time one-way alternating k-counter automata. (C) 2002 Elsevier Science B.V. All rights reserved.

关键词： iterative array cellular automata alternating counter automata

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ALGORITHMS FOR iterative array MULTIPLICATION

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IEEE TRANSACTIONS ON COMPUTERS 1986年第8期35卷 713-719页

作者： NAKAMURA, S Thayer School of Engineering Dartmouth College Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions

Algorithms for the parallel multiplication of two n- bit binary numbers by an iterative array of logic cells are discussed. The regular interconnection structures of the multiplier array cell elements, which are ideal for VLSI implementation, are described. The speed and hardware complexity of two new iterative array algorithms, both of which require n-cell delays for one n-bit × n-bit multiplication, are compared to a straightforward iterative array algorithm having a 2n-cell delay and its higher radix version having an n-cell delay.

关键词： Complexity five-counter iterative array multiplication speed parallel multiplication partial-products

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AUGMENTED iterative array FOR HIGH-SPEED BINARY DIVISION

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IEEE TRANSACTIONS ON COMPUTERS 1973年第2期C 22卷 172-175页

作者： CAPPA, M HAMACHER, VC COLLINS RADIO CO TORONTOONTARIOCANADA UNIV TORONTO DEPT ELECT ENGN & COMP SCITORONTOONTARIOCANADA

An augmented iterative array for binary division (IAD), is described. It uses carry-save reduction and carry-look-ahead principles to achieve high speed. Logic cost and speed comparisons with two other design techniques are presented. An 8-bit prototype model that operates in under 500 ns has been built from commercially available high-speed MSI TTL integrated circuits to verify the feasibility of the IAD scheme.

关键词： Division Network iterative array Nonrestoring Division

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Comments on "An Augmented iterative array for High Speed Division"

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IEEE Transactions on Computers 1974年第3期C-23卷 326-327页

作者： A.B. Gardiner R and D Laboratories Eurotherm Limited Lewes Sussex UK

Division is a serial operation and it is argued that parallel division arrays are unnecessary since serial circulating dividers can be designed which are almost as fast, when using the same technology, but are a fract... 详细信息

关键词： Division Network iterative array Serial Division

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TRUTH-TABLE VERIFICATION OF AN iterative LOGIC array

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IEEE TRANSACTIONS ON COMPUTERS 1976年第6期25卷 605-613页

作者： DIAS, FJO UNIV SAO PAULO ESCOLA POLITEC DEPT ELECT ENGN SAO PAULO BRAZIL

This paper studies the problem of fault detection in iterative logic arrays (ILA"s) made up of combinational cells arranged in a one-dimensional configuration with only one direction for signal propagation. It is assumed that a fault can change the behavior of the basic cell of the array in an arbitrary way, as long as the cell remains a combinational circuit. It is further assumed that any number of cells can be faulty at any time. In this way, testing an array is equivalent to verifying the correctness of its truth table. That could be done exhaustively through the application of a set of tests whose size is exponential in N, the number of cells in the array. The procedure presented in this paper generates a test set whose size is constant (i.e., independent of the number N of cells in the array). Conditions (on the structure of the basic cell) for the application of this procedure are presented. A practical example illustrating the application of this procedure is presented. Bounds for the size of the derived test set are presented and it is shown how to modify the basic cell of an arbitrary array in order to test it with a constant number of tests.

关键词： Adder cell checking experiment fault detection iterative array multiple fault test truth table.

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REAL-TIME COMPUTATION BY N-DIMENSIONAL iterative arrayS OF FINITE-STATE MACHINES

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IEEE TRANSACTIONS ON COMPUTERS 1969年第4期C 18卷 349-&页

作者： COLE, SN Federal Systems Division IBM Corporation Owego NY USA

An n-dimensional iterative array of finite-state machines is formally introduced as a real-time tape acceptor. The computational characteristics of iterative arrays are illuminated by establishing several results concerning the sets of tapes that they recognize. Intercommunication between machines in an array is characterized by specifying a stencil for the array. The computing capability of the array is preserved even if its stencil is reduced to a simple form in which machines communicate only with their nearest neighbors. An increase of computing speed by a constant factor k is defined by encoding k-length blocks of the input tapes, which reduces the lengths of the tapes by 1/k; the time available for computation is correspondingly reduced since the computation must be real time. The computation speed of iterative arrays can be increased by any constant factor k. Two examples of one-dimensional arrays are provided. The first accepts the set of palindromes; the second accepts the set of all tapes of the form ττ (for any tape τ). The latter set of tapes is not a context-free language; therefore, the sets of tapes accepted by iterative arrays are not all contained in the class of context-free languages. Conversely, the class of context-free languages is not contained in the class of sets of tapes accepted by iterative arrays. The sets of tapes accepted by iterative arrays are closed under the operations: union, intersection, and complement; therefore, they form a Boolean algebra. They are not closed under the reflection or concatenation-product operations.

关键词： Acceptor computation computing capability context-free language iterative array n-dimensional palindrome real time.

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MACHINE COMPLEXITY VERSUS INTERCONNECTION COMPLEXITY IN iterative arrayS

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IEEE TRANSACTIONS ON COMPUTERS 1971年第3期C 20卷 321-&页

作者： HAMACHER, VC IEEE Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions

A procedure is given for the construction of a von Neumann neighborhood iterative array to simulate a Moore neighborhood array in real time for the cases of up to three-dimensional arrays. The increase in the typical machine complexity accompanying this neighborhood complexity reduction is significantly less than that found in the general n-dimensional study of Cole [1].

关键词： array machine complexity iterative array real time stencil reduction.

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CAM-based array converter for URR floating-point arithmetic

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1998年第10期E81D卷 1120-1130页

作者： Lu, KM Tamaru, K Kyoto Univ Dept Elect & Commun Engn Kyoto 6068501 Japan

In order to lessen overflow or underflow problem in numerical computation, several new floating-point arithmetics have been proposed. The significant advantage of these new arithmetics is that a number can be represented in a wider range since the fields of exponent and mantissa are changed depending on the magnitude of number. The main issues of these arithmetics are how to find the boundary between exponent and mantissa as well as to convert the formats between new floating-point airthmetic and fixed-point arithmetic quickly. In this paper, a CAM-based array converter based on the Universal Representation of Real number (URR) floating-point airthmetic is described. Using match retrieval device CAM the detection of the boundary can be accomplished faster than conventional circuits. Arranging the basic cells into iterative array structure, the fast separation/connection operation is achieved. The speed, area and power consumption of the converter is estimated.

关键词： floating-point arithmetic content addressable memory iterative array URR format conversion

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PARALLEL PARSING ON A ONE-WAY array OF FINITE-STATE MACHINES

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IEEE TRANSACTIONS ON COMPUTERS 1987年第1期36卷 64-75页

作者： CHANG, JH IBARRA, OH PALIS, MA UNIV PENN DEPT COMP & INFORMAT SCI PHILADELPHIA PA 19104 USA UNIV MINNESOTA DEPT COMP SCI MINNEAPOLIS MN 55455 USA

We show that a one-way two-dimensional iterative array of finite-state machines (2-DIA) can recognize and parse strings of any context-free language in linear time. What makes this result interesting and rather surprising is the fact that each processor of the array holds only a fixed amount of information (independent of the size of the input) and communicates with its neighbors in only one direction. This makes for a simple VLSI implementation. Although it is known that recognition can be done on a 2-DIA, previous parsing algorithms require the processors to have unbounded memory, even when the communication is two-way. We also consider the problem of finding approximate patterns in strings, the string-to-string correction problem, and the longest common subsequence problem, and show that they can be solved in linear time on a 2-DIA.

关键词： Context-free language VLSI dynamic programming finite-state machine iterative array longest common subsequence parsing pattern matching sequence comparison

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PARTITIONED array FOR STABLE MATRIX TRIANGULARIZATION

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IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES 1986年第1期133卷 45-53页

作者： CIMINIERA, L SERRA, A VALENZANO, A Dipartimento di Automatica & Informatica Politecnico di Torino Torino Italy

The paper presents a new iterative array, which performs the triangularisation of a dense matrix, using the Givens rotation algorithm. Two slightly different arrays are presented: the first performs the factorisation of a single matrix; the second performs the recursive triangularisation. Partitioning of the first structure is also considered, in order to cope with matrices larger than the array. The implementation of the cell in the array is based on on-line arithmetic, which allows us to obtain high performances. Furthermore, the cell implementation requires only three types of arithmetic units (multiplication/addition, square root, division) and shift registers for data buffering and for generating the timing signals.

关键词： Logic circuits Logic and switching circuits timing signals generation data buffering VLSI factorisation stable matrix triangularisation Digital arithmetic methods digital arithmetic cellular arrays partitioned array dense matrix Givens rotation algorithm shift registers iterative array integrated circuit technology Semiconductor integrated circuits VLSI technology

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