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ACM SIGPLAN Conference on Object-oriented Programming, Systems, Languages, and Applications

作者： Toshio Suganuma Toshiaki Yasue Motohiro Kawahito Hideaki Komatsu Toshio Nakatani IBM Tokyo Research Laboratory 1623-14 Shimoturuma Yamato-shi Kanagawa 242-8502 Japan

ISBN: (纸本)1581133359

The high performance implementation of Java Virtual Machines (JVM) and just-in-time (JIT) compilers is directed toward adaptive compilation optimizations on the basis of online runtime profile information. This paper describes the design and implementation of a dynamic optimization framework in a production-level Java JIT compiler. Our approach is to employ a mixed mode interpreter and a three level optimizing compiler, supporting quick, full, and special optimization, each of which has a different set of tradeoffs between compilation overhead and execution speed. a lightweight sampling profiler operates continuously during the entire program's exectuion. When necessary, detailed information on runtime behavior is collected by dynmiacally generating instrumentation code which can be installed to and uninstalled from the specified recompilation target code. Value profiling with this instrumentation mechanism allows fully automatic code specialization to be performed on the basis of specific parameter values or global data at the highest optimization level. The experimental results show that our approach offers high performance and a low code expansion ratio in both program startup and steady state measurements in comparison to the compile-only approach, and that the code specialization can also contribute modest performance improvement

关键词： just in time compiler Java Java programming language HIGH-PERFORMANCE tradeoffs performance boost Runtime Codes Collected papers

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Compiling Java just in time

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IEEE MICRO 1997年第3期17卷 36-43页

作者： Cramer, T Friedman, R Miller, T Seberger, D Wilson, R Wolczko, M SUN MICROSYST INC MT VIEWCA 94043

The Java programming language promises portable, secure execution of applications. Early Java implementations relied on interpretation, leading to poor performance compared to compiled programs. Compiling Java programs to the native machine instructions provides much higher performance. Because traditional compilation would defeat Java's portability and security, another approach is necessary. This article describes some of the important issues related to just-in-time, or JIT, compilation techniques for Java. We focus on the JIT compilers developed by Sun for use with the JDK (Java Development Kit) virtual machine running on SPARC and Intel processors. (Access the Web at ***. com/workshop/java/jit for these compilers and additional information.) We also discuss performance improvements and limitations of JIT compilers. Future Java implementations may provide even better performance, and we outline some specific techniques that they may use.

关键词： just in time compiler Java programming language scalable processor architecture compilers Collected papers

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A Framework for Lattice QCD Calculations on GPUs

A Framework for Lattice QCD Calculations on GPUs

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IEEE 28th International Parallel & Distributed Processing Symposium (IPDPS)

作者： Winter, F. T. Clark, M. A. Edwards, R. G. Joo, B. Thomas Jefferson Natl Accelerator Facil Newport News VA 23606 USA NVIDIA Corp Santa Clara CA 95050 USA

ISBN: (纸本)9780769552071

Computing platforms equipped with accelerators like GPUs have proven to provide great computational power. However, exploiting such platforms for existing scientific applications is not a trivial task. Current GPU programming frameworks such as CUDA C/C++ require low-level programming from the developer in order to achieve high performance code. As a result porting of applications to GPUs is typically limited to time-dominant algorithms and routines, leaving the remainder not accelerated which can open a serious Amdahl's law issue. The Lattice QCD application Chroma allows us to explore a different porting strategy. The layered structure of the software architecture logically separates the data-parallel from the application layer. The QCD Data-Parallel software layer provides data types and expressions with stencil-like operations suitable for lattice field theory. Chroma implements algorithms in terms of this high-level interface. Thus by porting the low-level layer one effectively ports the whole application layer in one swing. The QDP-JIT/PTX library, our reimplementation of the low-level layer, provides a framework for Lattice QCD calculations for the CUDA architecture. The complete software interface is supported and thus applications can be run unaltered on GPU-based parallel computers. This reimplementation was possible due to the availability of a JIT compiler which translates an assembly language (PTX) to GPU code. The existing expression templates enabled us to employ compile-time computations in order to build code generators and to automate the memory management for CUDA. Our implementation has allowed us to deploy the full Chroma gauge-generation program on large scale GPU-based machines such as Titan and Blue Waters and accelerate the calculation by more than an order of magnitude.

关键词： Application framework C++ CUDA GPU JIT Lattice QCD PTX Lattice QCD GRAPPER PICK UP Graphics Processing Unit Application Framework just in time compiler data parallel application layer Store management LOW LEVEL Code generation Chroma Frameworks software interface

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Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator 15

Efficient Dual-ISA Support in a Retargetable, Asynchronous D...

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International Conference on Embedded Computer Systems Architectures Modeling and Simulation

作者： Spink, Tom Wagstaff, Harry Franke, Bjorn Topham, Nigel Univ Edinburgh Sch Informat Inst Comp Syst Architecture Edinburgh EH8 9YL Midlothian Scotland

ISBN: (纸本)9781467373111

Dynamic Binary Translation (DBT) allows software compiled for one Instruction Set Architecture (ISA) to be executed on a processor supporting a different ISA. Some modern DBT systems decouple their main execution loop from the built-in just-In-time (JIT) compiler, i.e. the JIT compiler can operate asynchronously in a different thread without blocking program execution. However, this creates a problem for target architectures with dual-ISA support such as ARM/THUMB, where the ISA of the currently executed instruction stream may be different to the one processed by the JIT compiler due to their decoupled operation and dynamic mode changes. In this paper we present a new approach for dual-ISA support in such an asynchronous DBT system, which integrates ISA mode tracking and hot-swapping of software instruction decoders. We demonstrate how this can be achieved in a retargetable DBT system, where the target ISA is not hard-coded, but a processor-specific module is generated from a high-level architecture description. We have implemented ARM V5T support in our DBT and demonstrate execution rates of up to 1148 MIPS for the SPEC CPU 2006 benchmarks compiled for ARM/THUMB, achieving on average 192%, and up to 323%, of the speed of QEMU, which has been subject to intensive manual performance tuning and requires significant low-level effort for retargeting.

关键词： just in time compiler DBT gene DESIGN BASIS TORNADOES Asynchronous instruction flow redirection translator Legal Executions

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Incremental JIT compiler for Implicitly Parallel Functional Language

Incremental JIT Compiler for Implicitly Parallel Functional ...

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Federated Conference on Computer Science and Information Systems (FedCSIS)

作者： Krajca, Petr Palacky Univ Dept Comp Sci CZ-77146 Olomouc Czech Republic

ISBN: (纸本)9781467344715

We present a novel method for automatic parallelization of functional programs which combines interpretation and just-in-time compilation. We propose an execution model for a Lisp-based programming language which involves a runtime environment which is able to identify portions of code worth running in parallel and is able to spawn new threads of execution. Furthermore, in order to achieve better performance, runtime environment dynamically identifies expressions worth compiling and compiles them into a native code.

关键词： Functional programming Operating Environment just in time compiler compilers Parallel Lines Codes Legal Executions Incremental

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Pydgin: Generating Fast Instruction Set Simulators from Simple Architecture Descriptions with Meta-Tracing JIT compilers 15

Pydgin: Generating Fast Instruction Set Simulators from Simp...

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IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

作者： Lockhart, Derek Ilbeyi, Berkin Batten, Christopher Cornell Univ Sch Elect & Comp Engn Ithaca NY 14850 USA

ISBN: (纸本)9781479919574

Instruction set simulators (ISSs) remain an essential tool for the rapid exploration and evaluation of instruction set extensions in both academia and industry. Due to their importance in both hardware and software design, modern ISSs must balance a tension between developer productivity and high-performance simulation. Productivity requirements have led to "ADL-driven" toolflows that automatically generate ISSs from high-level architectural description languages (ADLs). Meanwhile, performance requirements have prompted ISSs to incorporate increasingly complicated dynamic binary translation (DBT) techniques. Construction of frameworks capable of providing both the productivity benefits of ADL-generated simulators and the performance benefits of DBT remains a significant challenge. We introduce Pydgin, a new approach to ISS construction that addresses the multiple challenges of designing, implementing, and maintaining ADL-generated DBT-ISSs. Pydgin uses a Python-based, embedded-ADL to succinctly describe instruction behavior as directly executable "pseudocode". These Pydgin ADL descriptions are used to automatically generate high-performance DBT-ISSs by creatively adapting an existing meta-tracing JIT compilation framework designed for general-purpose dynamic programming languages. We demonstrate the capabilities of Pydgin by implementing ISSs for two instruction sets and show that Pydgin provides concise, flexible ISA descriptions while also generating simulators with performance comparable to hand-coded DBT-ISSs.

关键词： instruction sets simulator just in time compiler DBT gene DESIGN BASIS TORNADOES Activities of Daily Living AUTOMATIC productivity compilers Computer hardware

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VMKit: a Substrate for Managed Runtime Environments 10

VMKit: a Substrate for Managed Runtime Environments

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6th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments

作者： Geoffray, Nicolas Thomas, Gaeel Lawall, Julia Muller, Gilles Folliot, Bertil Univ Paris 06 INRIA Regal LIP6 Paris France Univ Copenhagen Copenhagen Denmark

ISBN: (纸本)9781605589107

Managed Runtime Environments (MREs), such as the JVM and the CLI, form an attractive environment for program execution, by providing portability and safety, via the use of a bytecode language and automatic memory management, as well as good performance, via just-in-time (JIT) compilation. Nevertheless, developing a fully featured MRE, including e. g. a garbage collector and JIT compiler, is a herculean task. As a result, new languages cannot easily take advantage of the benefits of MREs, and it is difficult to experiment with extensions of existing MRE based languages. This paper describes and evaluates VMKit, a first attempt to build a common substrate that eases the development of high-level MREs. We have successfully used VMKit to build two MREs: a Java Virtual Machine and a Common Language Runtime. We provide an extensive study of the lessons learned in developing this infrastructure, and assess the ease of implementing new MREs or MRE extensions and the resulting performance. In particular, it took one of the authors only one month to develop a Common Language Runtime using VMKit. VMKit furthermore has performance comparable to the well established open source MREs Cacao, Apache Harmony and Mono, and is 1.2 to 3 times slower than JikesRVM on most of the DaCapo benchmarks.

关键词： Design Performance Experimentation Virtual machine just in time compiler VMKit LLVM

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Experimental validation of IoT image encryption scheme based on a 5-D fractional hyperchaotic system and Numba JIT compiler

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INTERNET OF THINGS 2024年 25卷

作者： Clemente-Lopez, Daniel Munoz-Pacheco, Jesus M. Rangel-Magdaleno, Jose de Jesus Inst Nacl Astrofis Opt & Elect INAOE Dept Elect Luis Enrique Erro 1 Tonantzintla 72840 Puebla Mexico Benemerita Univ Autonoma Puebla Fac Elect Sci Ave San Claudio & 18 Sur Puebla 72570 Puebla Mexico

In the realm of Internet of Things (IoT) systems, the interconnectivity of physical hardware devices is a fundamental aspect, and as a result, data exchange assumes a critical role in the network. Given the sensitivity of such information, it is imperative to adopt appropriate measures to encrypt the data to safeguard it from unauthorized access. It is, therefore, paramount to prove novel encryption algorithms at an experimental level. To overcome that, a potential solution is fractional-order multi-scroll chaotic systems, which provide an extra degree of freedom to enhance ergodicity and random-like behaviors, which can help to improve encryption keyspace to get robust ciphers. However, the numerical algorithms to obtain a fractional chaotic series increase the computational cost because they demand extensive simulation time to model the memory of the standard fractional derivatives, limiting highspeed encryption. In this framework, a fast encryption scheme using a 5D fractional-order (FO) hyper-chaotic multi-scroll (HCMS) system is proposed and verified experimentally. Based on multiprocessing strategies and the Numba just -in -time (JIT) compiler, the Python code that describes the FO-HCMS system is optimized, which enables image encryption in real -time. The physical implementation of the encryption scheme is performed on an Advance RISC Machine (ARM) processor, and it is applied for image encryption on a machine-to-machine (M2M) communication using the message queuing telemetry transport (MQTT) protocol. The obtained results indicate that the proposed encryption scheme can reach encryption throughputs of up to 19.891 Mbps on an ARM with a 1.4 GHz CPU and 77.864 Mbps on a PC with a 3.1 GHz CPU.

关键词： Encryption algorithm Chaos Multi-scroll Fractional-order derivative ARM processor Multiprocessing just in time compiler Chaotic systems

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