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IS THERE A PLC ALTERNATIVE FOR INDUSTRY?

IFAC Proceedings Volumes 2006年第17期39卷 125-130页

作者： Ian Clark Sias Mostert University of Stellenbosch South Africa

Microprocessor improvements and cost reductions outpace industrial controllers without widespread industrial acceptance. Programmable logic controller popularity is due to rugged packaging, predictability, reasonable debug capability and widespread familiarity. Equipment life cycles involve machine building, commissioning, on-site upgrading and fault finding. An alternative high-performance platform suitable for development as well as during deployment is proposed for increasingly complex tasks such as high-speed packaging, motion control, robotics, networking and remote visualization that demand faster processors programmed in a common high-level language.

关键词： Industrial automation ladder algorithms Monitored control systems Programmable logic controllers Real-time

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Reinterpretation of the IEC 61131 ladder Diagram To Event Driven Program Based on the Dataflow Model

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IFAC Proceedings Volumes 2003年第1期36卷 13-18页

作者： Dariusz Choinski Technical University Gliwice Institute of Automatics

Methodology of dataflow models for systems simulation and analyzing are often used. Model of the simultaneously worked processors executing independent tasks may be used for simulation of the wide range systems with parallel processes structure. This is very important today for designing distributed control system. The most popular language of set of IEC 61131-3 languages is ladder Diagram. Such program allows transporting PLC programs from the programming environment of one vendor to another but the standard IEC 61131 no mechanism for data exchange between programming tools was defined. Reinterpretation and simulation based on the Dataflow model gives information about data exchange behaviors.

关键词： Programmable logic controllers ladder algorithms Distributed control systems Data flow analysis

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A Graph-Based Method to Translate Relay ladder Logic Diagrams

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IFAC Proceedings Volumes 1998年第4期31卷 35-40页

作者： J.L. Azevedo J.P. Estima De Oliveira Department of Electronics and Telecommunications University of Aveiro 3810 Aveiro Portugal Tlf. +351.34.370500

The Relay ladder Logic (RLL) graphic programming language is widely used to program Programmable Logic Controllers. A method to convert RLL diagrams into a set of Boolean expressions is presented. This method is based on the representation of each RLL network in terms of a directed graph. The original graph is reduced, in an iterative way, detecting and detaching parallel circuits by replacing groups of vertices by a single one. At the same time, each parallel circuit is independently translated. The logic expression for the reduced graph is then generated, and the final step is the recursive replacement of every reference to a parallel circuit by the sub-expression generated at reducing time.

关键词： Programmable Logic Controllers ladder algorithms Programming Languages Graphs

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EFFICIENT COVARIANCE ladder algorithms FOR FINITE ARITHMETIC APPLICATIONS

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SIGNAL PROCESSING 1987年第1期13卷 29-70页

作者： STROBACH, P SIEMENS AG Information Systems Laboratory ZT ZTI INF 121 D-8000 München 83 Fed. Rep. Germany

This paper is concerned with the problem of constructing numerically robust covariance ladder estimation algorithms for finite arithmetic applications. Conventional least-squares (LS) ladder algorithms suffer from mixed time and order recursive update equations resulting in a poor numerical accuracy when implemented with finite arithmetic. In this paper, a more ‘direct’ and numerically robust computation approach of the ladder update recursions using the most recently introduced algebraic method of generalized residual energies (GRE's) is presented. The new algorithms separate time and order recursions in two independent subalgorithms with a highly modular structure. Besides the general framework, five algorithms of this type are presented. Based on these algorithms, a VLSI ladder chip-set is proposed. Fixed-point simulations of the new VLSI structures are performed for several types of input data. The experimental analysis shows that the new algorithms are superior over conventional techniques and can operate at a multiplier wordlength as low as 8 bits. Dieser Aufsatz behandelt das Problem des Entwurfs numerisch robuster Kovarianz ladder Algorithmen für die Anwendung in Echtzeitrechnern mit beschränkter numerischer Genauigkeit. Konventionelle Least-Squares (LS) ladder Algorithmen basieren auf gemischt zeit- und ordnungsrekursiven Aktualisierungsgleichungen welche auf eine schlechte numerische Genauigkeit der Algorithmen führen. Eine erhebliche Verbesserung der numerischen Eigenschaften von ladder Algorithmen läβt sich mit Hilfe der neuen algebraischen Methode der verallgemeinerten Residualenergien (GRE's) erreichen, welche in diesem Aufsatz vorgestellt wird. Die aus dem neuen Ansatz resultierenden Verfahren erlauben die Trennung von Zeit- und Ordnungsrekursionen in zwei unabhängige Teilalgorithmen mit höchst modularer Struktur. Neben der allgemeinen Herleitung werden insgesamt fünf numerisch robuste ladder Algorithmen dieses Typs vorgestellt. Basierend auf diesen V

关键词： Autoregressive modeling ladder algorithms lattice algorithms VLSI realizations

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