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latency insertion method (LIM) for DC Analysis of Power Supply Networks

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 2011年第11期1卷 1839-1845页

作者： Klokotov, Dmitri Goh, Patrick Schutt-Aine, Jose E. Univ Illinois Dept Elect & Comp Engn Urbana IL 61801 USA

Process scaling in modern integrated circuits has led to multiple signal and power integrity issues. In particular, ensuring reliable performance of on-chip power delivery systems has become a major design challenge. Rigorous analysis and simulations are required at the design stage to ensure proper functionality of an on-chip power supply. This puts a strain on existing numerical tools due to the sheer size of the power grids. In this paper, a fast circuit simulation technique based on the latency insertion method (LIM) is proposed for the steady-state analysis of large-scale circuits, such as on-chip power distribution network. The proposed method is shown to be very efficient for modeling of networks with very large numbers of nodes. The comparison with one of the well-established methods used for the power grid analysis today, the Random-Walk algorithm, shows that LIM is almost two orders of magnitude faster.

关键词： DC analysis IR-drop latency insertion latency insertion method power distribution network power integrity power supply

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latency insertion method for FinFET Simulation Incorporating Parasitic Source/Drain Resistances 10

Latency Insertion Method for FinFET Simulation Incorporating...

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10th IEEE Electronics System-Integration Technology Conference (ESTC)

作者： Zhou, Yi Schutt-Aine, Jose E. Univ Illinois Dept Elect & Comp Engn Urbana IL 61820 USA

ISBN: (纸本)9798350390377;9798350390360

Three-dimensional FinFETs with well-suppressed short channel effects and low power consumption were introduced to replace traditional planar MOSFETs in sub-20 nm devices. However, the three-dimensional structure introduces numerous complex parasitic effects, which makes the simulation challenging. Developing fast and accurate simulation algorithms for FinFETs is thus critical to reduce verification time. The latency insertion method (LIM) proved to be able to provide accurate and fast FinFET DC simulation in our previous work. In this paper, we focus on improving the robustness of the algorithm by incorporating parasitic source/drain resistances. Following the BSIM-CMG compact model, we introduced the LIM schematics for three different parasitic resistance modes. The simulation results of LIM are compared with commercial simulators to verify the accuracy and speed.

关键词： latency insertion method FinFET BSIM-CMG compact model circuit simulation

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latency insertion method for Fast Electro-Thermal Simulation of FinFET with Self-Heating Effect 33

Latency Insertion Method for Fast Electro-Thermal Simulation...

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33rd Conference on Electrical Performance of Electronic Packaging and Systems

作者： Zhou, Yi Schutt-Aine, Jose E. Univ Illinois Dept Elect & Comp Engn Urbana IL 61801 USA

ISBN: (纸本)9798350351248;9798350351231

Self-heating effect (SHE) is prominent for FinFET devices due to their large currents and compact sizes. With SHE, the power in FinFETs is dissipated into heat, affecting device performance. Thus, fast and accurate electro-thermal analysis of FinFETs incorporating SHE is important. This paper proposes the latency insertion method (LIM) algorithm for fast FinFET electro-thermal simulation with SHE. Based on the BSIM-CMG model, the proposed method leapfrogs between the conventional electrical LIM algorithm and the thermal equations. The LIM results are compared to SPICE-based commercial software to prove the accuracy and the speed.

关键词： latency insertion method FinFET BSIM-CMG circuit simulation electro-thermal simulation self-heating effect

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latency insertion method for FinFET DC Operating Point Simulation Based on BSIM-CMG

Latency Insertion Method for FinFET DC Operating Point Simul...

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IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)

作者： Zhou, Yi Schutt-Aine, Jose E. Univ Illinois Dept Elect & Comp Engn Urbana IL 61801 USA

ISBN: (数字)9781665491945

ISBN: (纸本)9781665491945

As the scaling of planar MOSFETs progresses, various short-channel effects become prominent. The 3-dimensional FinFET was invented to avoid these short-channel effects. Transistor-level simulation with FinFETs is traditionally conducted by SPICE which has super-linear computational complexity. We propose a new method for FinFET DC operating point simulation through the use of the latency insertion method (LIM) which exhibits linear computational complexity. The algorithm incorporates the BSIM-CMG industry-standard compact model. The method is tested on 10 nm and 20 nm FinFETs, and the results are compared with commercial simulators.

关键词： latency insertion method FinFET BSIM-CMG compact model circuit simulation integrated circuit

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Partitioned latency insertion method With a Generalized Stability Criteria

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IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 2011年第9期1卷 1447-1455页

作者： Goh, Patrick Schutt-Aine, Jose E. Klokotov, Dmitri Tan, Jilin Liu, Ping Dai, Wenliang Al-Hawari, Feras Univ Illinois Dept Elect & Comp Engn Urbana IL 61801 USA Cadence Design Syst Inc Chelmsford MA 01824 USA

This paper presents a modular approach to the high-frequency simulation of large networks. By utilizing the latency insertion method (LIM) and by studying the stability criteria of partitions of different latencies in the circuit, a robust method is formulated that is able to perform transient simulations significantly faster than the conventional LIM method. The LIM method is also extended to handle dependent sources, and a general stability criterion for selecting the time step, independent of the topology of the circuit, is proposed. The new method is verified with existing commercial tools for circuit simulations, and the improvement in run time is also depicted.

关键词： Circuit simulation dependent sources latency insertion method partitioned latency insertion method stability

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Parallel electromagnetic transient simulation of power systems with a high proportion of renewable energy based on latency insertion method

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IET RENEWABLE POWER GENERATION 2023年第1期17卷 110-123页

作者： Wang, Qiguo Xu, Jin Wang, Keyou Wu, Pan Chen, Weiran Li, Zirun Shanghai Jiao Tong Univ Key Lab Control Power Transmiss & Convers Minist Educ Shanghai Peoples R China

With the interconnection of regional grids and the increasing penetration of renewable energy, the order of the power system model is getting higher and higher, which brings great challenges to the accuracy and real-time performance of electromagnetic transient (EMT) simulation. The simulation of power systems with a high proportion of renewable energy requires a sharp increase in the performance of the hardware platform and the parallelism of the simulation algorithm. To solve this problem, the paper proposes a fine-grained parallel modelling method for power systems with a high proportion of renewable energy, which is inspired by the latency insertion method used in the design of large-scale integrated circuits. And this method is implemented on GPU to achieve the component-level and device-level parallelized simulation of power systems with a high proportion of renewable energy. Finally, the correctness of the proposed algorithm and the CPU-GPU cooperative architecture is verified based on an improved 118-bus case. The cascade system of the improved 9-bus case is used as an example to verify the superiority of the proposed algorithm in terms of simulation efficiency.

关键词： Optimisation techniques Power system management, operation and economics parallel processing renewable energy fine-grained parallel modelling method device-level parallelized simulation simulation efficiency parallel electromagnetic transient simulation simulation algorithm Microprocessors and microcomputers cascade system power system simulation Power system control Microprocessor chips power system model power grids latency insertion method Power engineering computing Parallel software power systems graphics processing units EMTP

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Voltage-in-current formulation for the latency insertion method for improved stability

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ELECTRONICS LETTERS 2016年第23期52卷 1904-U12页

作者： Tan, K. H. Goh, P. Ain, M. F. Univ Sains Malaysia Sch Elect & Elect Engn Nibong Tebal 14300 Penang Malaysia

A new formulation for the latency insertion method (LIM) by implicitly substituting the voltages in the currents is presented. LIM is a fast transient analysis technique for large networks. However, due to its explicit formulation, it has a limitation on the time step size to guarantee numerical stability, similar to the finite-difference time-domain technique. This limits the efficiency of the method particularly where small parasitic inductances and capacitances are present which necessitates the use of very small time steps. Using the new formulation, an improved LIM is presented, where accurate and stable results can be obtained without limitation on the time step size.

关键词： circuit stability numerical stability transient analysis capacitance inductance network analysis voltage-in-current formulation latency insertion method improved stability LIM fast transient analysis numerical stability parasitic inductances parasitic capacitances

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Alternating Direction Explicit-latency insertion method (ADE-LIM) for the Fast Transient Simulation of Transmission Lines

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IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 2012年第5期2卷 783-792页

作者： Kurobe, Hiroki Sekine, Tadatoshi Asai, Hideki Shizuoka Univ Grad Sch Engn Dept Syst Engn Hamamatsu Shizuoka 4328561 Japan Shizuoka Univ Grad Sch Sci & Technol Dept Informat Sci & Technol Hamamatsu Shizuoka 4328561 Japan

This paper describes the alternating direction explicit-latency insertion method (ADE-LIM) for the fast simulations of transmission lines. LIM is one of the fast transient analysis techniques for large networks. However, because this method is based on an explicit finite-difference method, it has a limitation of the time step size for the numerical stability condition similar to the finite-difference time-domain technique. On the other hand, the ADE method is one of the finite-difference methods and has advantages of less computational complexity and numerical stability. In this paper, we propose ADE-LIM as an improved method of LIM. This method can circumvent the above time step limitation problem because the method is based on the ADE algorithm. Numerical results show that ADE-LIM is about 3-3.5 times faster than LIM in the transmission line analyses with appropriate accuracy.

关键词： Alternating direction explicit method interconnect networks latency insertion method multiconductor transmission lines time-domain analysis transmission line analysis

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Fast Transient Analysis of Power Distribution Network Modeled by Unstructured Meshes by Using Locally Implicit latency insertion method

Fast Transient Analysis of Power Distribution Network Modele...

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IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)

作者： Okada, Shingo Kurobe, Hiroki Sekine, Tadatoshi Asai, Hideki Shizuoka Univ Grad Sch Engn Dept Syst Eng Naka Ku 3-5-1 Johoku Hamamatsu Shizuoka 4328561 Japan Shizuoka Univ Johoku Dept Syst Eng Naka Ku Hamamatsu shi Shizuoka Japan

ISBN: (纸本)9781467314442;9781467314459

This paper proposes a locally implicit latency insertion method (LILIM), which is a suitable method for the fast simulation of an arbitrary shaped power distribution network (PDN) modeled by triangular meshes. First, an efficient modeling method based on triangular mesh is reviewed and we refer to the limitation of the LIM for the meshed PDN analysis. Next, in order to overcome the problem, we formulate the LILIM by combining the efficient modeling and the locally implicit schemes. Finally, the numerical results show that the LILIM is applicable and efficient for the simulation of the PDN analysis.

关键词： Delaunay triangular mesh latency insertion method locally implicit finite difference method power distribution network time-domain analysis Voronoi tessellation

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Fast Eye Diagram Simulation based on latency insertion method

Fast Eye Diagram Simulation based on Latency Insertion Metho...

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IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)

作者： Zhou, Yi Shi, Bobi Zhao, Yixuan Schutt-Aine, Jose E. Univ Illinois Dept Elect & Comp Engn Urbana IL 61801 USA

ISBN: (数字)9781665491945

ISBN: (纸本)9781665491945

Eye diagrams are used to assess the quality of highspeed channels. They are thus very important for signal integrity analysis. The voltage-in-current latency insertion method (VinC LIM) is a fast transient circuit simulation algorithm with superior stability properties. In this paper, VinC LIM is proven to be reliable for fast transient simulation of eye diagrams. The results and speed are compared with the transient simulation and channel simulation of commercial platforms.

关键词： latency insertion method circuit simulation eye diagram signal integrity high-speed link

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