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A novel hybrid authentication protocol utilizing lattice-based cryptography for IoT devices in fog networks

Digital Communications and Networks 2024年第4期10卷 989-1000页

作者： Kumar Sekhar Roy Subhrajyoti Deb Hemanta Kumar Kalita Department of Computer Science and Engineering Manipal Institute of Technology BengaluruManipal Academy of Higher EducationManipal576104KarnatakaIndia Department of Computer Science&Engineering ICFAI UniversityAgartala799210India Department of Computer Science&Engineering Central Institute of TechnologyKokrajhar783370India

The Internet of Things(IoT)has taken the interconnected world by *** to their immense applicability,IoT devices are being scaled at exponential proportions ***,very little focus has been given to securing such *** these devices are constrained in numerous aspects,it leaves network designers and administrators with no choice but to deploy them with minimal or no security at *** have seen distributed denial-ofservice attacks being raised using such devices during the infamous Mirai botnet attack in *** we propose a lightweight authentication protocol to provide proper access to such *** have considered several aspects while designing our authentication protocol,such as scalability,movement,user registration,device registration,*** define the architecture we used a three-layered model consisting of cloud,fog,and edge *** have also proposed several pre-existing cipher suites based on post-quantum cryptography for evaluation and *** also provide a fail-safe mechanism for a situation where an authenticating server might fail,and the deployed IoT devices can self-organize to keep providing services with no human *** find that our protocol works the fastest when using ring learning with *** prove the safety of our authentication protocol using the automated validation of Internet security protocols and applications *** conclusion,we propose a safe,hybrid,and fast authentication protocol for authenticating IoT devices in a fog computing environment.

关键词： Internet of things Authentication Post-quantum cryptography lattice-based cryptography Cloud computing Fog computing Fail-safe

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On Practical Discrete Gaussian Samplers for lattice-based cryptography

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IEEE TRANSACTIONS ON COMPUTERS 2018年第3期67卷 322-334页

作者： Howe, James Khalid, Ayesha Rafferty, Ciara Regazzoni, Francesco O'Neill, Maire Queens Univ Belfast CSIT Belfast BT7 1NN Antrim North Ireland Univ Svizzera Italiana Adv Learning & Res Inst CH-6900 Lugano Switzerland

lattice-based cryptography is one of the most promising branches of quantum resilient cryptography, offering versatility and efficiency. Discrete Gaussian samplers are a core building block in most, if not all, lattice-based cryptosystems, and optimised samplers are desirable both for high-speed and low-area applications. Due to the inherent structure of existing discrete Gaussian sampling methods, lattice-based cryptosystems are vulnerable to side-channel attacks, such as timing analysis. In this paper, the first comprehensive evaluation of discrete Gaussian samplers in hardware is presented, targeting FPGA devices. Novel optimised discrete Gaussian sampler hardware architectures are proposed for the main sampling techniques. An independent-time design of each of the samplers is presented, offering security against side-channel timing attacks, including the first proposed constant-time Bernoulli, Knuth-Yao, and discrete Ziggurat sampler hardware designs. For a balanced performance, the Cumulative Distribution Table (CDT) sampler is recommended, with the proposed hardware CDT design achieving a throughput of 59.4 million samples per second for encryption, utilising just 43 slices on a Virtex 6 FPGA and 16.3 million samples per second for signatures with 179 slices on a Spartan 6 device.

关键词： lattice-based cryptography post-quantum cryptography discrete Gaussian sampling hardware security cryptography

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Revisiting Higher-Order Masked Comparison for lattice-based cryptography: Algorithms and Bit-Sliced Implementations

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IEEE TRANSACTIONS ON COMPUTERS 2023年第2期72卷 321-332页

作者： D'Anvers, Jan-Pieter Van Beirendonck, Michiel Verbauwhede, Ingrid Katholieke Univ Leuven Imec COSIC Leuven Belgium

Marked comparison is one of the most expensive operations in side-channel secure implementations of lattice-based post-quantum cryptography, especially for higher masking orders. First, we introduce two new masked comparison algorithms, which improve the arithmetic comparison of D'Anvers et al. (2021) and the hybrid comparison method of Coron et al. (2021) respectively. We then look into implementation-specific optimizations, and show that small specific adaptations can have a significant impact on the overall performance. Finally, we implement various state-of-the-art comparison algorithms and benchmark them on the same platform (ARM-Cortex M4) to allow a fair comparison between them. We improve on the arithmetic comparison of D'Anvers et al. with a factor asymptotic to 20% by using Galois Field multiplications and the hybrid comparison of Coron et al. with a factor asymptotic to 25% by streamlining the design. Our implementation-specific improvements allow a speedup of a straightforward comparison implementation of asymptotic to 33%. We discuss the differences between the various algorithms and provide the implementations and a testing framework to ease future research.

关键词： Encryption Arithmetic Security Side-channel attacks Costs Standards NIST Post-quantum cryptography lattice-based cryptography side-channel protection masking

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Sparse polynomial multiplication for lattice-based cryptography with small complexity

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JOURNAL OF SUPERCOMPUTING 2016年第2期72卷 438-450页

作者： Akleylek, Sedat Alkim, Erdem Tok, Zaliha Yuce Tech Univ Darmstadt Cryptog & Comp Algebra Grp Darmstadt Germany Ondokuz Mayis Univ Dept Comp Engn Samsun Turkey Ege Univ Dept Math Izmir Turkey Middle E Tech Univ Inst Appl Math TR-06531 Ankara Turkey

In this paper, we propose efficient modular polynomial multiplication methods with applications in lattice-based cryptography. We provide a sparse polynomial multiplication to be used in the quotient ring (Z/pZ)[x]/(x(n) + 1). Then, we modify this algorithm with sliding window method for sparse polynomial multiplication. Moreover, the proposed methods are independent of the choice of reduction polynomial. We also implement the proposed algorithms on the Core i5-3210M CPU platform and compare them with number theoretic transform multiplication. According to the experimental results, we speed up the multiplication operation in (Z/pZ)[x]/(x(n) + 1) at least 80% and improve the performance of the signature generation and verification process of GLP scheme significantly.

关键词： Polynomial multiplication lattice-based cryptography Sparse polynomial Sliding window method Software implementation

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Exploring Energy Efficient Architectures for RLWE lattice-based cryptography

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2021年第10期93卷 1139-1148页

作者： Nejatollahi, Hamid Shahhosseini, Sina Cammarota, Rosario Dutt, Nikil Univ Calif Irvine Irvine CA 92697 USA Intel AI Privacy & Secur Res Hillsboro OR USA

Quantum computers are imminent threat to secure signal processing because they can break the contemporary public-key cryptography schemes in polynomial time. Ring learning with error (RLWE) lattice-based cryptography (LBC) is considered as the most versatile and efficient family of post-quantum cryptography (PQC). Polynomial multiplication is the most compute-intensive routine in the RLWE schemes. Convolutions and Number Theoretic Transform (NTT) are two common methods to perform the polynomial multiplication. In this paper, we explore the energy efficiency of different polynomial multipliers, NTT-based and convolution-based, on GPU and FPGA. When synthesized on a Zynq UltraScale+ FPGA, our NTT-based and convolution-based designs achieve on average 5.1x and 22.5x speedup over state-of-the-art. Our convolution-based design, on a Zynq UltraScale+ FPGA, can generate more than 2x signatures per second by CRYSTALS-Dilithium. The designed NTT-based multiplier on NVIDIA Jetson TX2 is 1.2x and 2x faster than our baseline NTT-based multiplier on FPGA for polynomial degrees of 512 and 1024, respectively. Our explorations and guidelines can help designers choose proper implementations to realize quantum-resistant signal processing.

关键词： Public key cryptography lattice-based cryptography Acceleration Number theoretic transform Systolic array

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High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to lattice-based cryptography

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IEEE TRANSACTIONS ON COMPUTERS 2023年第9期72卷 2454-2466页

作者： Tan, Weihang Wang, Antian Zhang, Xinmiao Lao, Yingjie Parhi, Keshab K. K. Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA Clemson Univ Dept Elect & Comp Engn Clemson SC 29634 USA Ohio State Univ Dept Elect & Comp Engn Columbus OH 43210 USA

This paper presents a low-latency hardware accelerator for modular polynomial multiplication for lattice-based post-quantum cryptography and homomorphic encryption applications. The proposed novel modular polynomial multiplier exploits the fast finite impulse response (FIR) filter architecture to reduce the computational complexity of the schoolbook modular polynomial multiplication. We also extend this structure to fast $M$M-parallel architectures while achieving low-latency, high-speed, and full hardware utilization. We comprehensively evaluate the performance of the proposed architectures under various polynomial settings as well as in the Saber scheme for post-quantum cryptography as a case study. The experimental results show that our proposed modular polynomial multiplier reduces the computation time and area-time product, respectively, compared to the state-of-the-art designs.

关键词： Fast filtering homomorphic encryption high-speed lattice-based cryptography polyphase decomposition Parallel modular polynomial multiplication post-quantum cryptography systolic array saber cryptosystem

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TensorCrypto: High Throughput Acceleration of lattice-based cryptography Using Tensor Core on GPU

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IEEE ACCESS 2022年 10卷 20616-20632页

作者： Lee, Wai-Kong Seo, Hwajeong Zhang, Zhenfei Hwang, Seong Oun Gachon Univ Dept Comp Engn Seongnam 13120 South Korea Hansung Univ Coll IT Engn Seoul 02876 South Korea Ethereum Fdn CH-6300 Zug Switzerland

Tensor core is a newly introduced hardware unit in NVIDIA GPU chips that allows matrix multiplication to be computed much faster than in the integer and floating-point units. In this paper, we show that for the first time, tensor core can be used to accelerate state-of-the-art lattice-based cryptosystems. We employed tensor core to speed up polynomial convolution, which is the most time consuming operation in lattice-based cryptosystems. Towards that aim, several parallel algorithms are proposed to allow the tensor core to handle flexible matrix sizes and ephemeral key pairs. Experimental results show that the polynomial convolution computed using the tensor core is at least 2x faster than the version implemented with conventional integer units of the NVIDIA GPU. The proposed tensor-core-based polynomial convolution technique was applied to NTRU, one of the finalists in NIST post-quantum cryptography (PQC) standardization. It achieved 2.02 x/1.98 x (encapsulation) and 1.56x/1.90 x (decapsulation) higher throughput on two parameter sets (ntruhps2048509 and ntruhps2048677), compared to the conventional integer-based implementations on a GPU. In particular, the proposed implementation techniques achieved throughput up to 793651 key encapsulations per second and 505051 decapsulations per second on a RTX2060 GPU. To demonstrate the flexibility of the proposed technique, we extend the implementation to other lattice-based cryptosystems that have a small modulus: LAC and two variant parameter sets in FrodoKEM. Considering that the IoT gateway devices and cloud servers need to handle massive connections from the sensor nodes, the proposed high throughput implementation on GPU is very useful in securing the IoT communication.

关键词： cryptography convolution lattice-based cryptography tensor core graphics processing units information security polynomial convolution

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Configurable Mixed-Radix Number Theoretic Transform Architecture for lattice-based cryptography

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IEEE ACCESS 2022年 10卷 12732-12741页

作者： Phap Duong-Ngoc Lee, Hanho Inha Univ Dept Informat & Commun Engn Incheon 22212 South Korea

lattice-based cryptography continues to dominate in the second-round finalists of the National Institute of Standards and Technology post-quantum cryptography standardization process. Computational efficiency is primarily considered to evaluate promising candidates for final round selection. In lattice-based cryptosystems, polynomial multiplication is the most expensive computation and critical to improve the performance. This paper proposes an efficient number theoretic transform (NTT) architecture to accelerate the polynomial multiplication. The proposed design applies mixed-radix multi-path delay feedback architecture and flexibly adopts various polynomial sizes. Configurable NTT design is realized to perform forward and inverse NTT computations on a unified hardware, which is then used to develop an efficient polynomial multiplier. The proposed architectures were successfully accelerated on several Xilinx FPGA platforms to directly compare with state-of-the-art works. The implementation results show that the proposed NTT architectures have comparable area-time product and demonstrate 1.7 similar to 17x performance improvement, and the proposed polynomial multipliers achieve higher performance compared with previous works. Experimental results confirmed the proposed design's applicability for high-speed large-scale data cryptoprocessors.

关键词： lattice-based cryptography number theoretic transform mixed-radix multi-path delay feedback post-quantum cryptography

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An efficient and light weight polynomial multiplication for ideal lattice-based cryptography

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MULTIMEDIA TOOLS AND APPLICATIONS 2021年第2期80卷 3089-3120页

作者： Yadav, Vijay Kumar Verma, Shekhar Venkatesan, S. Indian Inst Informat Technol Allahabad Devghat Allahabad 211015 UP India

Ring-Learning With Errors (Ring-LWE) based cryptographic schemes such as signature, key exchange, and encryption require polynomial multiplication. This multiplication operation is the most time consuming and computationally rigorous process in Ring-LWE. In order to improve the efficiency of the Ring-LWE based schemes, most of the existing schemes use Fast Fourier Transform (FFT) based polynomial multiplication algorithm. It is known that Discrete Sine Transformation (DST) and Discrete Cosine Transformation (DCT) are faster than the FFT. The combination of DCT and DST is Discrete Trigonometric Transform (DTT). When we generalize DTT in terms of FFT form, it becomes Generalized Discrete Fourier Transform (GDFT). In this paper, we propose two new polynomial multiplication techniques using DTT and GDFT. When we applycircular convolutionandskew-circular convolutionon DTT or GDFT for the polynomial multiplication, it gives us wrong results. To overcome this issue, we usesymmetric convolutionoperation on DTT and GDFT. We implemented and compared the proposed polynomial multiplication schemes with the current state-of-the-art schemes in terms of computation and communication costs. The implementation results show that the proposed schemes DTT and GDFT perform more efficiently as compared to current state-of-the-art schemes in terms of computation and communication costs.

关键词： Fast fourier transform Discrete cosine transformation Number theoretic transform lattice-based cryptography Ring-learning with errors

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The implementation of polynomial multiplication for lattice-based cryptography: A survey

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JOURNAL OF INFORMATION SECURITY AND APPLICATIONS 2024年 83卷

作者： Zeng, Chenkai He, Debiao Feng, Qi Peng, Cong Luo, Min Wuhan Univ Sch Cyber Sci & Engn Key Lab Aerosp Informat Secur & Trusted Comp Minist Educ Wuhan 430072 Peoples R China Qilu Univ Technol Shandong Acad Sci Shandong Comp Sci Ctr Key Lab Comp Power Network & Informat SecurMinist Jinan 250014 Peoples R China Shanghai Technol Innovat Ctr Distributed Privacy P Matrix Elements Technol Shanghai 200232 Peoples R China

The advent of quantum computing threatens the security of traditional public -key cryptography. Algorithms for quantum computing have the ability to solve the large prime factorization and the discrete logarithm problem in polynomial time. To deal with the threat, post -quantum cryptography (PQC) primitives and protocols were proposed. lattice -based cryptography (LBC) is the promising post -quantum cryptography, both in traditional and emerging security scenarios such as public -key encryption, homomorphic encryption and oblivious transfer. Theoretically, the algebraic structure of the lattice provides a secure fundamental for LBC. In contrast, the implementation should consider the balance of time, space, and resources for realization on various programmable platforms. In the implementation of lattice -based cryptography, polynomial multiplication is the primary operation accounting for about 30% of the execution. To improve the performance of LBC schemes, various efficient algorithms have been proposed over decades. This work focuses on approaches to accelerate polynomial multiplication used in LBC schemes. First, we review and compare three polynomial multiplication algorithms, Number Theory Transform (NTT), Karatsuba algorithm and Toom-Cook algorithm. Then we present a comprehensive survey of implementation on programmable platforms such as Graphics Processing Unit (GPU) and Field -Programmable Gate Array (FPGA). At last, we summarize the future trend of implementing polynomial multiplication and provide recommendations.

关键词： lattice-based cryptography Polynomial multiplication Implementation Karatsuba Toom-Cook NTT GPU FPGA

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