Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon limit. However, their different code str...
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ISBN:
(纸本)9781424429233
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon limit. However, their different code structures usually lead to different hardware implementations. In this paper, we propose a unified decoder architecture that is capable of decoding both LDPC and turbo codes with a limited hardware overhead. We employ maximum a posteriori (map) algorithm as a bridge between LDPC and turbo codes. We represent LDPC codes as parallel concatenated single parity check (PCSPC) codes and propose a group sub-trellis (GST) decoding algorithm for the efficient decoding of PCSPC codes. This algorithm achieves about 2X improvement in the convergence speed and is more numerically robust than the classical "tanh" algorithm. What is more interesting is that we can generalize a unified trellis decoding algorithm for LDPC and turbo codes based on their trellis structures. We propose a reconfigurable computation kernel for log-map decoding of LDPC and turbo codes at a cost of similar to 15% hardware overhead. Small lookup tables (LUTs) with 9 entries of 2-bit data are designed to implement the log-map algorithm. Fixed point (6:2) simulation results show that there is negligible or nearly no performance loss by using this LUT approximation compared to the ideal case. The proposed architecture results in scalable and flexible datapath units enabling parallel decoding of LDPC/turbo codes.
As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper presents an efficient reverse calculati...
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As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper presents an efficient reverse calculation method to lower the power consumption by reducing the number of memory accesses required in turbo decoding. The reverse calculation method is proposed for the Max-log-map algorithm, and it is combined with a scaling technique to achieve a new decoding algorithm, called hybrid log-map, that results in a similar BER performance to the log-map algorithm. For the W-CDMA standard, experimental results show that 80% of memory accesses are reduced through the proposed reverse calculation method. A hybrid log-map turbo decoder based on the proposed reverse calculation reduces power consumption and memory size by 34.4% and 39.2%, respectively.
A new pipelined parallel architecture for turbo decoding is presented. It runs at nearly four times the speed of the traditional architecture with tolerable hardware resource increasing. The bottleneck in turbo decode...
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ISBN:
(纸本)9781424403868
A new pipelined parallel architecture for turbo decoding is presented. It runs at nearly four times the speed of the traditional architecture with tolerable hardware resource increasing. The bottleneck in turbo decoder is the Add-Compare-Select-Offset (ACSO) unit used in forward and backward recursive state metrics (FRSM, BRSM) calculation. In the new architecture the critical path in ACSO unit is divided into four shorter evenly parts by inserting four register vectors, which improves the working frequency of the turbo decoder. And the sliding window architecture is modified to make use of the new ACSO unit. At the same time, the received symbol sequence is divided into four evenly pieces, that are fed into the same ACSO unit one after another to form the pipeline. Then the speed of turbo decoder will be approximately four times as the old one.
Turbo codes represent a very powerful channel coding technique for next generation of mobile communications. In our days, the research is focus on the development and implementation of turbo coding-decoding algorithms...
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ISBN:
(纸本)0769522831
Turbo codes represent a very powerful channel coding technique for next generation of mobile communications. In our days, the research is focus on the development and implementation of turbo coding-decoding algorithms in high-speed programmable platforms (DSP's and FPGA's) for a better performance in terms of error correction, power consumption and speed AMP (Maximum A-posteriori probability) algorithm represents the best performance choice for turbo decoding block. The main objective of implementation is to design structures for turbo decoding near to the theoretical performances using sub-optimal architectures. In this work we present a hardware implementation of the log-domain version of the AMP algorithm (log-AMP). This version of the algorithm gives an excellent approach to the Shannon limits and allows the description of simple blocks based on arithmetic operators, like MAX* operator.
Bit-interleaved turbo-coded modulation is more sensitive to signal-to-noise ratio (SNR) overestimation than turbo code with BPSK. An explanation is given from the effect of SNR mismatch on bit-metric generation, which...
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Bit-interleaved turbo-coded modulation is more sensitive to signal-to-noise ratio (SNR) overestimation than turbo code with BPSK. An explanation is given from the effect of SNR mismatch on bit-metric generation, which consequently affects the log-map turbo-decoding algorithm.
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