检索结果-内蒙古大学图书馆

A tunable high-performance architecture for enhancement of stream video captured under non-uniform lighting conditions

引用

MICROPROCESSORS AND MICROSYSTEMS 2008年第7期32卷 386-393页

作者： Zhang, Ming Z. Seow, Ming-Jung Tao, Li Asari, Vijayan K. Old Dominion Univ Dept Elect & Comp Engn Computat Intelligence & Machine Vis Lab Norfolk VA 23529 USA

A novel architecture for performing hue-saturation-value (HSV) domain enhancement of digital color images captured under non-uniform lighting conditions is proposed in this paper for video streaming applications. The approach promotes log-domain computation to eliminate all multiplications, divisions and exponentiations utilizing the compact high-speed logarithmic estimation modules. An optimized quadrant symmetric architecture is incorporated into the design of homomorphic filter for the enhancement of intensity value. Efficient modules are also presented for conversion between RGB and HSV color spaces with tunable H and S components in HSV for more flexible color rendering. The design is able to bring out details hidden in shadow regions of the image and preserve the bright parts with adjustable vividness and color shift for improvement of visual quality while maintaining its consistency. It is capable of producing 187.86 million outputs per second (MOPs) on Xilinx's Virtex II XC2V2000-4ff896 field programmable gate array (FPGA) at a clock frequency of 187.86 MHz. It can process over 179.1 (1024 x 1024) frames per second, which is very suitable for high definition videos, and consumes approximately 70.7% and 76.8% less hardware resource with 127% and 280% performance boost when compared to the designs with machine learning algorithm in [M.Z. Zhang, M.J. Seow, V.K. Asari, A high performance architecture for color image enhancement using a machine learning approach, International journal of computational intelligence Research - Special Issue on Advances in Neural Networks 2(1) (2006) 40-47], and with separated dynamic and contrast enhancements in [H.T. Ngo, M.Z. Zhang, L. Tao, V.K. Asari, Design of a high performance architecture for real-time enhancement of video stream captured in extremely low lighting environment, International journal of Embedded Systems: Special Issue on Media and Stream Processing, in press], respectively. This approach also provide 83.4 time

关键词： Nonlinear color image enhancement Reflectance-illuminance model HSV-domain components rendering Color space conversion log-domain computation 2D convolution Parallel-pipelining Multiplier-less architecture Homomorphic filter Quadrant symmetric architecture

来源：评论

学校读者我要写书评

暂无评论

Design of an efficient flexible architecture for color image enhancement

Design of an efficient flexible architecture for color image...

引用

11th Asia-Pacific Conference on Advances in Computer Systems Architecture

作者： Zhang, Ming Z. Tao, Li Seow, Ming-Jung Asari, Vijayan K. Old Dominion Univ Dept Elect & Comp Engn Computat Intelligence & Machine Vis Lab Norfolk VA 23529 USA

ISBN: (纸本)3540400567

A novel architecture for performing digital color image enhancement based on reflectance/illumination model is proposed in this paper. The approach promotes the log-domain computation to eliminate all multiplications, divisions and exponentiations utilizing the approximation techniques for efficient estimation of 1092 and inverse-1092. A new quadrant symmetric architecture is also incorporated into the design of homomorphic filter to achieve very high throughput rate which is part of V component enhancement in Hue-Saturation-Value (HSV) color space. The pipelined design of the filter features the flexibility in reloading a wide range of kernels for different frequency responses. A generalized architecture of max/min filter is also presented for efficient extraction of V component. With effective color space conversion, the HSV-domain image enhancement architecture is able to achieve a throughput rate of 182.65 million outputs per second (MOPS) or equivalently 52.8 billion operations per second on Xilinx's Virtex II XC2V2000-4ff896 field programmable gate array (FPGA) at a clock frequency of 182.65 MHz. It can process over 174.2 mega-pixel (1024 x 1024) frames. per second and consumes approximately 70.7% less hardware resource when compared to the design presented in [10].

关键词： color image enhancement reflectance/illumination model HSV-domain image processing log-domain computation 2D convolution multiplier-less architecture homomorphic filter quadrant symmetric architecture parallel-pipelined architecture

来源：评论

学校读者我要写书评

暂无评论

A design methodology for performance-resource optimization of a generalized 2D convolution architecture with quadrant symmetric kernels

A design methodology for performance-resource optimization o...

引用

12th Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007)

作者： Zhang, Ming Z. Asari, Vijayan K. Old Dominion Univ Dept Elect & Comp Engn Computat Intelligence & Machine Vis Lab Norfolk VA 23529 USA

ISBN: (纸本)9783540743088

We present a design technique to meet application driven constraints for performance-resource optimization of a generalized 2D convolution with quadrant symmetric kernels. A fully pipelined multiplierless digital architecture for computing modularized 2D convolution utilizing the quadrant symmetry of the kernels is proposed in this paper. Pixels in the four quadrants of the kernel region with respect to an image pixel are considered simultaneously with distributed queues for computing the partial results of the convolution sum in time-sliced fashion. The new architecture performs computations in log-domain by utilizing low complexity high performance log(2) and inverse-log(2) estimation modules. An effective data handling strategy is developed to minimize routing of data path in conjunction with the logarithmic modules to eliminate the necessity of the multipliers in the architecture. The proposed architecture is capable of performing convolution operations for 45.5 (1024x1024) frames or 47.73 million outputs per second in minimum resource configuration with 8x8 kernels in a Xilinx's Virtex XC2V2000-4ff896 field programmable gate array (FPCA) at maximum clock frequency of 190.92 MHz. Analysis shows that the performance and resource utilization between the fully parallel and fully resource constrained architectures are proportional to f and 1/f, respectively where f is the application driven reusability of the main computing components. In addition to resource reduction from optimization scheme, evaluation in Xilinx's core generator also showed that the proposed design results in 60% reduction in hardware when compared to the design using pipelined multipliers.

关键词： 2D convolution log-domain computation multiplier-less architecture quadrant symmetric kernels modularized optimization FPGA based architecture

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：