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检索条件"主题词=logic arrays"

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Interleaved logical Qubits in Atom arrays

Interleaved Logical Qubits in Atom Arrays

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IEEE Symposium on High-Performance Computer Architecture

作者： Joshua Viszlai Sophia Lin Siddharth Dangwal Conor Bradley Vikram Ramesh Jonathan Baker Hannes Bernien Frederic T. Chong University of Chicago University of Texas Austin

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Neutral atom arrays have seen exciting progress as a platform for quantum computation. However, as we move towards the regime of fault-tolerance, the large-scale impact of fundamental features in these systems is not well-studied. In this work we point out that the use of movement in neutral atom arrays may set an unavoidable constraint on the speed of computation, erasing potential quantum advantage. As one solution, we propose a movement-free QEC architecture based on groups of interleaved surface codes. Our architecture enables fast, high-fidelity transversal CNOTs on surface codes in the same group. We also introduce interleaved lattice surgery to create high-capacity routing channels between groups. We validate our architecture through detailed numerical simulations of the underlying circuits and we evaluate its scalability through compilation of key benchmark applications. In regimes of high parallelism, we find our architecture leads to a $\sim 3 \times$ reduction in compute time. Our architecture leverages experimentally demonstrated dualspecies atom arrays which exhibit asymmetric interaction strengths that scale with $1 / r^{3}$ for interspecies interactions and with $1 / r^{6}$ for standard, intraspecies interactions. We examine how such scalings enable interleaving with high fidelity and propose how error rates required for QEC could be achieved. We also evaluate the tolerance of our architecture to two-qubit gate fidelities. We find the advantage of interleaving admits sizable tolerances of $\sim 1 \times$ to $3 \times$ increase in error rates. We conclude the benefits of our proposed interleaved architecture grants strong motivation for future experimental efforts targeting longer range dual-species gates.

关键词： Codes Qubit Surgery Lattices Computer architecture logic gates Parallel processing Routing Standards logic arrays

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DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement

DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Da...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Chuyu Wang Ke Hu Fan Yang Keren Zhu Xuan Zeng State Key Laboratory of Integrated Chips and Systems School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Digital computing-in-memory (DCIM) systems integrate complex digital logic with parasitic-sensitive bitcell arrays. Conventional physical design strategies degrade DCIM performance due to a lack of dataflow regularity and excessive wirelength. As a result, current DCIM design often relies on manual layout, which is time-consuming and a bottleneck in the design cycle. Existing layout synthesis frameworks for DCIM often mimic the manual approach and employ a template-based method for DCIM placement. However, overly constrained templates lead to an excessive core area, resulting in high costs in practice. In this work, we introduce DAMIL-DCIM, a novel placement framework that bridges template-based techniques with optimization-based placement methods. DAMIL-DCIM utilizes a global dataflow-aware floorplan inspired by template methods and further optimizes the layout using MILP(Mixed Integer Linear Programming)-based detailed placement. The combination of global floorplanning and placement optimization reduces total wire length while maintaining dataflow regularity, resulting in lower parasitic and enhanced performance. Experimental results show, on a practical 28nm DCIM circuit, our approach improves frequency by 25.2% and reduces power consumption by 19.6% compared to Cadence Innovus, while maintaining the same core area.

关键词： Measurement Power demand Layout Manuals In-memory computing Wire logic Optimization logic arrays Physical design

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OpenC2: An Open-Source End-to-End Hardware Compiler Development Framework for Digital Compute-in-Memory Macro

OpenC2: An Open-Source End-to-End Hardware Compiler Developm...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Tianchu Dong Shaoxuan Li Yihang Zuo Hongwu Jiang Yuzhe Ma Shanshi Huang Microeletronics Thrust The Hong Kong University of Science and Technology (Guangzhou) Guangzhou China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Digital Compute-in-Memory (DCIM), which inserts logic circuits into SRAM arrays, presents a significant advancement in CIM architecture. DCIM has shown great potential in applications, and the diversity of applications requires rapid hardware iteration. However, the hardware design flow from user specifications to layout is extremely tedious and time-consuming for manual design. Commercial EDA tools are limited by restrictive licenses and the inability to specifically optimize the datapath, which calls for an open-source end-to-end hardware compiler for DCIM. This paper proposes $\mathbf{O}\mathbf{p}\mathbf{e}\mathbf{n}\mathbf{C}^{2}$ , the first open-source end-to-end development framework for DCIM macro compilation. $\mathbf{O}\mathbf{p}\mathbf{e}\mathbf{n}\mathbf{C}^{2}$ provides a template-based generation platform for DCIM macros across various technologies, sizes, and configurations. It can automatically generate a datapath-optimized, compact DCIM macro layout based on a hierarchical physical design methodology. Our experiment results show that $\mathbf{O}\mathbf{p}\mathbf{e}\mathbf{n}\mathbf{C}^{2}$ 's compact design on FreePDK45 delivers over 30% area reduction and over 40% improvement in area efficiency compared to AutoDCIM on TSMC40.

关键词： Layout Random access memory Europe Manuals Licenses In-memory computing Hardware Common Information Model (computing) logic arrays Physical design

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Optimal Synthesis of Memristive Mixed-Mode Circuits

Optimal Synthesis of Memristive Mixed-Mode Circuits

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Design, Automation and Test in Europe Conference and Exhibition

作者： Ilia Polian Xianyue Zhao Li-Wei Chen Felix Bayhurst Ziang Chen Heidemarie Schmidt Nan Du University of Stuttgart Institute of Computer Architecture and Computer Engineering Stuttgart Germany Department of Quantum Detection Friedrich Schiller University Jena Institute for Solid State Physics Leibniz Institute of Photonic Technology Jena Germany

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Memristive crossbars are attractive for in-memory computing due to their integration density combined with compute and storage capabilities of their basic devices. However, yield and fidelity of emerging memristive technologies can make their reliable operation unattainable, thus raising interest in simpler topologies. In this paper, we consider synthesis of Boolean functions on 1D memristive line arrays. We propose an optimal procedure that can fully utilize the rich electrical behavior of memristive devices, mixing stateful (resistance-input) and non-stateful (voltage-input) operations as desired by the designer, leveraging their respective strengths. The synthesis method is based on Boolean satisfiability (SAT) solving and supports flexible constraints to enforce, e.g., restrictions of the available peripher-als. We experimentally validate memristive logic circuits beyond individual logic gates by demonstrating the operation of a Galois field multiplier using a 1D line array of 10 memristors in parallel, highlighting the robust performance of our proposed mixed-mode circuit and its synthesis procedure.

关键词： Boolean functions Memristors Europe logic gates In-memory computing Topology logic Reliability Galois fields logic arrays

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SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis

SynDCIM: A Performance-Aware Digital Computing-in-Memory Com...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Kunming Shao Fengshi Tian Xiaomeng Wang Jiakun Zheng Jia Chen Jingyu He Hui Wu Jinbo Chen Xihao Guan Yi Deng Fengbin Tu Jie Yang Mohamad Sawan Tim Kwang-Ting Cheng Chi-Ying Tsui The Hong Kong University of Science and Technology Hong Kong SAR China AI Chip Center for Emerging Smart Systems (ACCESS) Hong Kong SAR China Westlake University Hangzhou China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Digital Computing-in-Memory (DCIM) is an innovative technology that integrates multiply-accumulation (MAC) logic directly into memory arrays to enhance the performance of modern AI computing. However, the need for customized memory cells and logic components currently necessitates significant manual effort in DCIM design. Existing tools for facilitating DCIM macro designs struggle to optimize subcircuit synthesis to meet user-defined performance criteria, thereby limiting the potential system-level acceleration that DCIM can offer. To address these challenges and enable the agile design of DCIM macros with optimal architectures, we present SynDCIM - a performance-aware DCIM compiler that employs multi-spec-oriented subcircuit synthesis. SynDCIM features an automated performance-to-layout generation process that aligns with user-defined performance expectations. This is supported by a scalable subcircuit library and a multi-spec-oriented searching algorithm for effective subcircuit synthesis. The effectiveness of SynDCIM is demonstrated through extensive experiments and validated with a test chip fabricated in a 40nm CMOS process. Testing results reveal that designs generated by SynDCIM exhibit competitive performance when compared to state-of-the-art manually designed DCIM macros.

关键词： Limiting Design automation Europe Manuals Computer architecture Libraries logic Artificial intelligence logic arrays Testing

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A 38Mb/mm2 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology

A 38Mb/mm2 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology

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IEEE International Conference on Solid-State Circuits (ISSCC)

作者： Harold Pilo John Barth Kapil Dev Dwivedi Peter Lee Vikram Kumar Prasanna Nalawar Yogeshbhai Patel Shailendra Sharad Shakti Singh Synopsys Williston VT Synopsys Noida India Synopsys Sunnyvale CA Synopsys Bangalore India

ISBN: (数字)9798331541019

ISBN: (纸本)9798331541026

This paper describes a 3nm-FinFET high-density SRAM compiler with an interface dual-rail (IDR) architecture to enable SoC operation down to 380mV, the lowest SRAM interface voltage reported to date. The SRAM achieves a density of 38Mb/mm2, the highest 1-port SRAM density reported to date. The lOR architecture enables the SRAM ${V}_{{DD}}$ interface to go as low as the shared SoC ${V}_{{DD}}$ standard logic, unrestricted by SRAM internal operations or the SRAM bitcell array supply voltage, ${V}_{{DDA}}$ The lowest possible SoC power can be achieved by supporting the lowest possible standard logic operational ${V}_{{DDMIN}}$ without impacting SRAM functionality or yield. level-shifting performance and area penalties typical of dual-rail designs are minimized with the lOR architecture. Key design features include an extended-range level shifter (ERLS), an integrated input latch and ERLS, a clock buffer with hig ${h}$ -voltage level-shift bypass, and an integrated output latch and level-shifter (LS). The SRAM compiler generates instances up to 1.3Mb capacity, which can be used for SoC memory applications such as a shared multi-CPU L3-data cache.

关键词： Latches Random access memory Voltage Solid state circuits logic Standards logic arrays Clocks

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Fault Testing in AI-Accelerators: A Review

Fault Testing in AI-Accelerators: A Review

引用

Asian Test Symposium (ATS)

作者： Bhargab B. Bhattacharya Debesh K. Das Subhajit Chatterjee Hafizur Rahaman ACM Unit Indian Statistical Institute Kolkata India Computer Science & Engg. Dept. Jadavpur University India Kolkata India School of VLSI Technology Indian Institute of Engineering Sc. and Tech. Howrah India

ISBN: (数字)9798331529161

ISBN: (纸本)9798331529178

With the emergence of all-inclusive AI/ML applications, hardware solutions, commonly known as AI-Accelerators (AIA), are now being widely adopted to emulate deep neural networks (DNN) to facilitate faster and large-scale data analytics. An AIA-chip comprises a 2D systolic array of identical processing units (PEs), registers, and glue logic. These arrays may be implemented with traditional digital logic or with analog primitives such as memristors. As the packing density of AIA-chips increases, they become vulnerable to various manufacturing defects thereby compromising yield and the accuracy of prediction. In this review article, we summarize various methods that have been recently proposed for expediting Automatic Test-Pattern Generation (ATPG) for stuck-at and transition faults in AIA-arrays. Other relevant issues such as fault-criticality, self-test, fault-recovery, and the asymmetry of fault behavior, are also discussed.

关键词： Data analysis Reviews Memristors Artificial neural networks Systolic arrays Hardware Registers Manufacturing logic logic arrays

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Atomic Cache: Enabling Efficient Fine-Grained Synchronization with Relaxed Memory Consistency on GPGPUs Through In-Cache Atomic Operations

Atomic Cache: Enabling Efficient Fine-Grained Synchronizatio...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Yicong Zhang Mingyu Wang Wangguang Wang Yangzhan Mai Haiqiu Huang Zhiyi Yu Sun Yat-sen University Guangzhou China

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

General-purpose graphics processing unit (GPGPU), widely recognized as an exceptional computing platform for de-ploying emerging parallel applications, requires strict adherence to atomicity and memory consistency models for shared variable synchronization. This is crucial to ensure deterministic execution and leverage the performance advantages of the GPGPU single-instruction -multiple-threads architecture. However, the escalating demand for shared variable updates across thread blocks, notably in applications like deep neural networks and graph analysis, significantly exacerbates the serialization overhead of atomic operations due to the von Neumann bottleneck. Additionally, the overhead introduced by memory fences supporting the memory consistency model further complicates this fine-grained synchronization requirement. To address these challenges, this paper proposes Atomic Cache, facilitating an In-Cache computing hardware-software co-design for GPGPUs. At the software level, we propose relaxed memory consistency based on non-ordering commutativity to alleviate the execution of in-cache atomic operations, thereby mitigating the performance overhead of memory fences. At the hardware level, we present the In-Situ Store Atomic Cache Macro, which empowers the Atomic Cache to efficiently execute atomic logic and arithmetic operations within the cache array. This innovation alleviates the von Neumann bottleneck associated with serialized execution of atomic operations. The experimental evaluation results demonstrate that the Atomic Cache can save more than 60% of memory access energy while incurring only 9.42% chip area overhead. Furthermore, it not only delivers an average speedup ratio of 2.59 × and an IPC performance improvement of 1.48× for RISC-V GPGPUs, but also achieves an average speedup ratio of 1.31 × and an IPC performance improvement of 39.92% when compared to state-of-the-art designs employing local atomic buffers.

关键词： Technological innovation Microarchitecture Computational modeling Memory management Graphics processing units Random access memory Software Synchronization logic logic arrays

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A High-Density RRAM-Based Ising Machine with Analog In-Memory Operation for Solving Combinatorial Optimization Problems

A High-Density RRAM-Based Ising Machine with Analog In-Memor...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Jingxin Deng Keji Zhou Honghu Yang Chengshuo Yu Jianguo Yang School of Microelectronics Frontier Institute of Chip and System Fudan University Shanghai China Zhangjiang Laboratory Shanghai China

ISBN: (数字)9798350356830

ISBN: (纸本)9798350356847

This work presents a Resistive RAM (RRAM)-based Ising machine characterized by high spin density and efficient analog in-memory computing. The proposed design enables compact spin representations that support interactions with up to eight neighboring spins at 1-bit precision. The functionality and performance of the proposed Ising machine is evaluated using comprehensive simulation in 28nm CMOS technology, incorporating measured RRAM variation characteristics to validate its robustness and efficiency. Additionally, software-based simulations are employed to solve classical combinatorial problems, such as the Max-Cut problem, while accounting for the non-idealities inherent in the proposed RRAM-based analog in-memory computing approach. Each proposed spin occupies an area of 13.5 μm 2 , achieving an area reduction of 16.7% to 92.1% compared to recent works, based on feature size normalization.

关键词： Circuits and systems Scalability Resistive RAM Simulated annealing In-memory computing Robustness Transistors Optimization logic arrays Convergence

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An SRAM-Based Multi-Operand Architecture Implementing Multi-Bit Boolean Functions Using in-Memory Periphery Computing

An SRAM-Based Multi-Operand Architecture Implementing Multi-...

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International Conference on VLSI Design

作者： Dhayan Dhananjaya Senanayake Priyanshu Tyagi Sparsh Mittal Rekha Singhal Indian Institute of Technology Roorkee TCS Reserach

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

This paper introduces a highly scalable in-memory computing architecture for implementing (1) $M$ -operand, $N$ -bit Boolean functions, viz., AND/NAND/NOR/OR, (2) any arbitrary Boolean function expressed as the sum of products (e.g., F=AB'CD+ABC'D'), (3) $N$ parallel 2-bit XOR operations. Our technique performs operations using a modified 9T SRAM cell-based peripheral circuitry near the SRAM array. Unlike conventional 9T SRAM designs that use the same bitlines for both read and write operations, our design introduces dedicated read lines to separate the read and write paths. This separation improves efficiency and allows in-memory implementation of complex Boolean operations. To implement $M$ -operand, $N$ -bit AND/OR operations, the periphery circuit has $N$ compute blocks, each with $M$ columns. The compute block stores the input operands along with configuration bits to choose the correct operation. An equality checker circuit compares the input operands with configuration bits to obtain original or complemented input. The outputs of equality checkers of different columns are connected to a product line, and by DeMorgan's theorem, either AND/NAND or NOR/OR can be realized. Using TSMC 65nm PDK in Cadence Virtuoso, we have demonstrated 64-bit AND/NAND/OR/NOR operations and 64 parallel 2-bit XOR operations. At 0.7V VDD, our design consumes 24.5fJ/bit and operates at 660MHz for XOR operations and 384MHz for other operations.

关键词： Boolean functions Simulation Scalability Random access memory Computer architecture Very large scale integration Energy efficiency logic Standards logic arrays

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