Graphene plasmonic logic gates (GPLGs) with high compaction and simple structure are presented and investigated in this paper. Due to the strong confinement of edge mode graphene surface plasmon polaritons (EGSPPs), i...
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Graphene plasmonic logic gates (GPLGs) with high compaction and simple structure are presented and investigated in this paper. Due to the strong confinement of edge mode graphene surface plasmon polaritons (EGSPPs), it can process optical signal on nanoscale ribbons with both straight and flexible shapes. Three eigen modes of graphene surface plasmon polaritons (GSPPs) are studied from the aspect of their propagation properties, indicating that the symmetric edge-mode (SEM) is an optimal choice for designing the GPLGs. Finally, some basic logic gates, i.e., the XOR and XNOR gates, are demonstrated by employing the SEM. More kind of GPLGs and functional devices are expected to be realized by cascading these basic logic gates.
We propose and experimentally demonstrate alloptical canonical logic units and wavelength conversion at 40 Gb/s by using four-wave mixing in a single highly nonlinear fiber. These results are achieved in seven paralle...
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ISBN:
(纸本)9781509062904
We propose and experimentally demonstrate alloptical canonical logic units and wavelength conversion at 40 Gb/s by using four-wave mixing in a single highly nonlinear fiber. These results are achieved in seven parallel channels simultaneously.
We present an all-optical packet buffer system that enables variable delay of the incoming packets in the optical domain based on the controllable-delay recirculating loop. It consists of two opticallogic gate stages...
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We present an all-optical packet buffer system that enables variable delay of the incoming packets in the optical domain based on the controllable-delay recirculating loop. It consists of two opticallogic gate stages based on cross gain modulation nonlinear effect of semiconductor optical amplifiers to control the amount of delay. Incoming optical packets were either stored in the recirculating loop or routed to the system output by an optical control signal. The validity of the system has been experimentally verified using the optical bit sequences operating at 1 Gbps. (C) 2014 Wiley Periodicals, Inc.
We propose and demonstrate all-optical simultaneous half-addition and half-subtraction of two return-to-zero on-off keying data streams using only two semiconductor optical amplifiers and without any assist light. In ...
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We propose and demonstrate all-optical simultaneous half-addition and half-subtraction of two return-to-zero on-off keying data streams using only two semiconductor optical amplifiers and without any assist light. In the experimental demonstration, we realize the arithmetic functions with an extinction ratio larger than 14 dB and achieve error-free signal processing at the repetition rate of 10 Gbit/s.
Two areas of intense current research, opticallogic and silicon photonics, can be combined to create opticallogic in silicon substrates. We describe a generic (universal) opticallogic gate based on silicon componen...
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Two areas of intense current research, opticallogic and silicon photonics, can be combined to create opticallogic in silicon substrates. We describe a generic (universal) opticallogic gate based on silicon components that can be programmed electronically to perform any logical operation on light beams confined in a silicon waveguide under control of the silicon electronics on the same chip. The effect is to create enhanced integration between optics and electronics. (c) 2006 Elsevier B.V. All rights reserved.
In this work, a three-step modified signed-digit (MSD) addition by using binary logic operations is proposed. Each input digit is encoded with two binary bits. Through binary logic operations, all of the weight and tr...
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In this work, a three-step modified signed-digit (MSD) addition by using binary logic operations is proposed. Each input digit is encoded with two binary bits. Through binary logic operations, all of the weight and transfer digits and the final sum digits represented with the same encoding scheme will be generated. The operations can be performed at each digit position in parallel. In our suggested optical arithmetic and logic unit (ALU), a single electron trapping (ET) device is employed to serve its the binary logic device. This technique based on ET logic possesses the advantage of high signal-to-noise ratio (SNR). The optoelectronic system can be constructed in a simple. compact and general-purpose form. (C) 2000 Elsevier Science Ltd. All rights reserved.
A compact two-step modified-signed-digit arithmetic-logic array processor is proposed. When the reference digits are programmed, both addition and subtraction can be performed by the same binary logic operations regar...
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ISBN:
(纸本)0819432911
A compact two-step modified-signed-digit arithmetic-logic array processor is proposed. When the reference digits are programmed, both addition and subtraction can be performed by the same binary logic operations regardless of the sign of the input digits. The optical implementation and experimental demonstration using an electron-trapping device are shown. Each digit is encoded by a single pixel, and no polarization is included. Any combinational logic can be easily performed without optoelectronic and electro-optic conversions of the intermediate results. The system is compact, general-purpose, simple to align and has a high signal-to-noise ratio.
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