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检索条件"主题词=loop level parallelism"

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Improving Performance of Simple Cores by Exploiting loop-level parallelism through Value Prediction and Reconfiguration 09

Improving Performance of Simple Cores by Exploiting Loop-Lev...

引用

6th ACM International Conference on Computing Frontiers and Workshops

作者： Suri, Tameesh Aggarwal, Aneesh SUNY Binghamton ECE Dept Binghamton NY 13902 USA

ISBN: (纸本)9781605584133

There is a growing trend towards designing simpler CPU cores that have considerable area, complexity, and power advantages. These cores are then leveraged in large-scale multicore processors or in SoCs for hand-held devices. The most significant limitation of such simple CPU cores is their lower performance. In this paper, we propose a technique to improve the performance of simple cores with minimal increase in complexity and area. In particular, we integrate a Reconfigurable Hardware Unit (RHU) that exploits loop-level parallelism to increase the core's overall performance. The RHU is reconfigured to execute instructions with highly predictable operand values front the future iterations of loops. Our experiments show that the proposed architecture improves the performance by an average of about 51% across a wide range of applications, while incurring a area overhead of only about 5.6%.

关键词： Dynamic Reconfiguration loop level parallelism Data Value Prediction

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loopapalooza: Investigating Limits of loop-level parallelism with a Compiler-Driven Approach

<i>Loopapalooza</i>: Investigating Limits of Loop-Level Para...

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IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

作者： Zaidi, Ali Mustafa Iordanou, Konstantinos Lujan, Mikel Gabrielli, Giacomo Arm Res Cambridge England Univ Manchester Dept Comp Sci Manchester Lancs England

ISBN: (纸本)9781728186436

Improving sequential performance of out-of-order processors is becoming harder. Further improvements may require exploitation of thread-level parallelism, on top of ILP, as it can provide better design and performance scaling. Unfortunately, previous "speculative multithreading" approaches have shown small gains and/or incur a high cost, particularly for general-purpose, non-numeric applications. This paper investigates the fundamental limits to sequential performance scaling through speculative multithreading - we present an LLVM compiler-driven limit study framework that investigates the limits of loop-level parallelism at run-time. This new study of loop-level parallelism demonstrates the potential for up to 4.6x and 7.2x geometric mean speedup on SpecINT2000 and SpecINT2006. Thanks to the additional consideration of recent parallelization schemes, such as generalized DOACROSS (HELIX), these potential speedups are higher than reported by previous state-of-the-art limit studies. Our analysis further categorizes the various inter-thread dependencies and ordering constraints with respect to the specific architectural choices and techniques each would require for implementation. We then evaluate the relative importance of each such constraint for different application (benchmark) types, and provide insight into the cost/benefit trade-offs when designing systems for efficiently implementing speculative multithreading. Such insights should help the design of bespoke systems for speculative multithreading while achieving better speedups, efficiency, and scaling, relative to typical approaches which, thus far, have relied upon adapting conventional multi-core systems.

关键词： Speculative Multithreading Thread level Speculation loop level parallelism Auto-parallelization LLVM

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loop transformation techniques to aid in loop unrolling and multithreading 16

Loop transformation techniques to aid in loop unrolling and ...

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16th International Conference on Parallel and Distributed Computing Systems (PDCS 2003)

作者： Song, LT Zhang, YH Kavi, K Univ N Texas Denton TX 76203 USA

ISBN: (纸本)188084348X

In modern computer. systems loops present a great deal of opportunities for increasing Instruction level and Thread level parallelism. loop Unrolling is a technique used to obtain greater ILP while independent loop iterations are assigned to different threads to obtain greater TLP. However, techniques are needed to avoid unnecessary checks to assure that only the correct number of iterations are executed. In this paper we evaluate simple loop transformation techniques that can improve the performance by eliminating. some unnecessary conditional instructions checking for iteration bounds. We present information on the number of instructions eliminated as well as on the improved branch prediction rates, and execution performance improvements. Our techniques are applicable to most modern architecture including superscalar, multithreaded, VLIW or EPIC systems.

关键词： ILP TLP loop level parallelism branch prediction code transformation

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Parallelizing Sequential Applications on Commodity Hardware using a Low-cost Software Transactional Memory 09

Parallelizing Sequential Applications on Commodity Hardware ...

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ACM SIGPLAN Conference on Programming Language Design and Implementation

作者： Mehrara, Mojtaba Hao, Jeff Hsu, Po-Chun Mahlke, Scott Univ Michigan Adv Comp Architecture Lab Ann Arbor MI 48109 USA

ISBN: (纸本)9781605583921

Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performance for most applications. The industry has already fallen short of the decades-old performance trend of doubling performance every 18 months. An attractive approach for exploiting multiple cores is to rely on tools, both compilers and runtime optimizers, to automatically extract threads from sequential applications. However, despite decades of research on automatic parallelization, most techniques are only effective in the scientific and data parallel domains where array dominated codes can be precisely analyzed by the compiler. Thread-level speculation offers the opportunity to expand parallelization to general-purpose programs, but at the cost of expensive hardware support. In this paper, we focus on providing low-overhead software support for exploiting speculative parallelism. We propose STMlite, a light-weight software transactional memory model that is customized to facilitate profile-guided automatic loop parallelization. STMlite eliminates a considerable amount of checking and locking overhead in conventional software transactional memory models by decoupling the commit phase from main transaction execution. Further, strong atomicity requirements for generic transactional memories are unnecessary within a stylized automatic parallelization framework. STMlite enables sequential applications to extract meaningful performance gains on commodity multicore hardware.

关键词： Software transactional memory Automatic parallelization Thread-level speculation loop level parallelism Profile-guided optimization

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Compiler and Runtime Techniques for Automatic Parallelization of Sequential Applications

Compiler and Runtime Techniques for Automatic Parallelizatio...

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作者： Mehrara, Mojtaba University of Michigan

学位级别：Ph.D.

Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performance for most applications. An attractive approach for exploiting multiple cores is to rely on tools, both compilers and runtime optimizers, to automatically extract threads from sequential applications. This dissertation tackles many challenges faced in automatic parallelization of sequential applications, including general-purpose applications written in C/C++ and client-side web applications written in JavaScript, with the goal of achieving speedup on commodity multicore systems. First, a complete parallelizing compiler system for C/C++ is introduced. This system successfully identifies parallelization opportunities in programs and transforms the code to a parallel version. A matching runtime system, STMlite, is proposed to monitor the parallelized program behavior and fix any misspeculations that might happen. We show that this system can generate and execute parallel programs that are upto 2.2x faster than their sequential counterparts, when executed on an 8-core commodity system. The second piece of work focuses on a similar problem in a very different application domain, JavaScript programs running on the client's web browser. This dissertation is the first research work that proposes dynamic and automatic parallelization of JavaScript applications. The nature of the JavaScript language and its target execution environments impose a completely different set of challenges that we intend to solve. We first propose the ParaScript parallelizing engine, which identifies and speculatively parallelizes potentially parallel code segments while the code is running in the browser. A low-cost and highly customized speculation approach verifies the execution of the parallelized client-side code and rolls back in case of any misspeculation. Dynamic parallelization using ParaScript yields an averag

关键词： Speculative Parallelization Software Transactional Memory JavaScript Parallelization Multicore Compilation Dynamic Parallelization loop level parallelism Thesis

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An Improving Computation and Data Decomposition Method

An Improving Computation and Data Decomposition Method

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2006年国际电子、工程及科学领域的分布式计算和应用学术研讨会

作者： Chunli Dong,RongcaiZhao,Jianmin Pang,Lin Han,Peng Du National Digital Switching System Engineering & Technology R &D Center Zhengzhou 450002,P.R CHINA

Data locality is critical to achieving high performance on high-performance parallel *** how to find a good data decomposition is becoming a key issue in parallelizing *** have developed a compiler system that fully automatically parallelizes sequential programs and optimizes data decomposition to improve data *** data decomposition algorithm consists of two *** first step chooses the basic data and computation decomposition without considering read-only *** second step then changes the data decomposition considering read-only data. We ran our compiler on a set of application *** results show that the algorithm can effectively discovers parallelism.

关键词： data decomposition computation decomposition read-only data loop level parallelism

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