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loop scheduling and bank type assignment for heterogeneous multi-bank memory

JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2009年第6期69卷 546-558页

作者： Qiu, Meikang Guo, Minyi Liu, Meiqin Xue, Chun Jason Yang, Laurence T. Sha, Edwin H. -M. Univ New Orleans Dept Elect & Comp Engn New Orleans LA 70148 USA Shanghai Jiao Tong Univ Dept Comp Sci & Engn Shanghai Peoples R China Zhejiang Univ Coll Elect Engn Hangzhou 310027 Peoples R China City Univ Hong Kong Dept Comp Sci Hong Kong Hong Kong Peoples R China St Francis Xavier Univ Dept Comp Sci Antigonish NS B2G 2W5 Canada Univ Texas Dallas Dept Comp Sci Richardson TX 75083 USA

Many high-performance DSP processors employ multi-bank on-chip memory to improve performance and energy consumption. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. However, making effective use of multi-bank memory remains difficult, considering the combined effect of performance and energy requirement. This paper studies the scheduling and assignment problem about how to minimize the total energy consumption while satisfying the timing constraint with heterogeneous multi-bank memory for applications with loop. An algorithm, TASL (Type Assignment and scheduling for loops), is proposed. The algorithm uses bank type assignment with the consideration of variable partition to find the best configuration for both memory and ALU. The experimental results show that the average improvement on energy-saving is significant by using TASL. (C) 2009 Elsevier Inc. All rights reserved.

关键词： Type assignment Heterogeneous Low power design Multi-bank memory loop scheduling

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Energy-Aware loop scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2009年第3期57卷 363-379页

作者： Qiu, Meikang Liu, Meiqin Li, Hao Huang, Hung-Chung Li, Wenyuan Wu, Jiande Univ New Orleans Dept Elect & Comp Engn New Orleans LA 70148 USA Zhejiang Univ Coll Elect Engn Hangzhou 310027 Peoples R China Univ N Texas Dept Comp Sci & Engn Denton TX 76203 USA Texas A&M Hlth Sci Ctr Dept Syst Biol & Translat Med Temple TX USA Univ So Calif Program Mol & Computat Biol Los Angeles CA USA

Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for applications with loops on multi-core, multi-Functional-Unit (multi-FU) architectures. An algorithm, EMPLS (Energy Minimization with Probability using loop scheduling), is proposed to minimize the total energy (E) while satisfying timing constraint (L) with guaranteed probability (P). We perform scheduling and assignment simultaneously. Our approach shows better performance than the approaches that consider scheduling and assignment in separate phases. Compared with previous work, our algorithm exhibits significant improvement in total energy reduction.

关键词： Assignment loop scheduling Multi-core Optimization Real-time

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Interprocedural analysis for loop scheduling and data allocation

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PARALLEL COMPUTING 1998年第3-4期24卷 477-504页

作者： Nguyen, TN Li, ZY Purdue Univ Dept Comp Sci W Lafayette IN 47907 USA IBM Corp Rochester MN 55906 USA

In order to reduce remote memory accesses on CC-NUMA multiprocessors, we present an interprocedural analysis to support static loop scheduling and data allocation. Given a parallelized program, the compiler constructs graphs which represent globally and interprocedurally the remote reference penalties associated with different choices for loop scheduling and data allocation. After deriving an optimal solution according to those graphs, the compiler generates data allocation directives and schedules DOALL loops. Experiments indicate that the proposed compiler scheme is efficient and simulation results show good performance of the parallel code. (C) 1998 Elsevier Science B.V. All rights reserved.

关键词： parallelizing compilers shared memory multiprocessors non-uniform memory access data allocation loop scheduling interprocedural analysis

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USING PROCESSOR AFFINITY IN loop scheduling ON SHARED-MEMORY MULTIPROCESSORS

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1994年第4期5卷 379-400页

作者： MARKATOS, EP LEBLANC, TJ UNIV ROCHESTER DEPT COMP SCIROCHESTERNY 14627

loops are the single largest source of parallelism in many applications. One way to exploit this parallelism is to execute loop iterations in parallel on different processors. Previous approaches to loop scheduling attempted to achieve the minimum completion time by distributing the workload as evenly as possible while minimizing the number of synchronization operations required. In this paper, we consider a third dimension to the problem of loop scheduling on shared-memory multiprocessors: communication overhead caused by accesses to nonlocal data. We show that traditional algorithms for loop scheduling, which ignore the location of data when assigning iterations to processors, incur a significant performance penalty on modern shared-memory multiprocessors. We propose a new loop scheduling algorithm that attempts to simultaneously balance the workload, minimize synchronization, and co-locate loop iterations with the necessary data. We compare the performance of this new algorithm to other known algorithms by using five representative kernel programs on a Silicon Graphics multiprocessor work-station, a BBN Butterfly, a Sequent Symmetry, and a KSR-1, and show that the new algorithm offers substantial performance improvements, up to a factor of 4 in some cases. We conclude that loop scheduling algorithms for shared-memory multiprocessors cannot afford to ignore the location of data, particularly in light of the increasing disparity between processor and memory speeds.

关键词： loop scheduling SYNCHRONIZATION LOAD IMBALANCE, COMMUNICATION OVERHEAD SHARED-MEMORY MULTIPROCESSORS

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Using Timed Petri Net to Model Instruction-Level loop scheduling with Resource Constraints

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Journal of Computer Science & Technology 1994年第2期9卷 128-143页

作者：王剑苏伯珙 INRIARocquencourt DomainedeVoluceauBP10578158LeChesnayCedexFrance

This paper uses timed Petri net to model and analyze the problem of instructionlevel loop scheduling with resource constraints, which has been proven to be an NP complete problem. First, we present a new timed Petri net model to integrate functional unit allocation, register allocation and spilling ilno a unified theoretical *** we develop a state subgraph, called Register Allocation Solution Graph, which can effectively describe the major behavior of our new model. The maill property of this state subgraph is that the number of all its nodes is polynomial. Finally we present and prove that the optimum loop schedules can be found with polynomial computation complexity, for almost all practical loop prograrns. Our work lightens a new idea of finding the optimum loop schedules.

关键词： Instruction level parallelism loop scheduling register allocation and spilling Petri net timed Petri net

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Compiler-assisted leakage-aware loop scheduling for embedded VLIW DSP processors

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JOURNAL OF SYSTEMS AND SOFTWARE 2010年第5期83卷 772-785页

作者： Wang, Meng Wang, Yi Liu, Duo Qin, Zhiwei Shao, Zili Hong Kong Polytech Univ Dept Comp Kowloon Hong Kong Peoples R China

As feature size shrinks, leakage energy consumption has become an important concern. In this paper, we develop a compiler-assisted instruction-level scheduling technique to reduce leakage energy consumption for applications with loops on VLIW architecture. In the proposed technique, we obtain the schedule with minimum leakage energy from the ones that are generated by repeatedly regrouping a loop based on rotation scheduling and bipartite-matching. We conduct experiments on a set of benchmarks from DSPstone, Mediabench, Netbench, and MiBench based on the power model of the VLIW processors. The results show that our algorithm can achieve significant leakage energy saving compared with the previous work. (C) 2009 Elsevier Inc. All rights reserved.

关键词： Leakage power loop scheduling VLIW architecture DSP applications

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A Compressed Data Partition and loop scheduling Scheme for Neural Networks

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IEEE ACCESS 2022年 10卷 95219-95228页

作者： Li, Dejian Fang, Rongqiang Wang, Jing Zhao, Dongyan Chong, Ting Ren, Zengmin Ma, Jun Beijing Smartchip Microelect Technol Co Ltd Beijing 100192 Peoples R China Beijing Jiaotong Univ Sch Comp & Informat Technol Beijing 100044 Peoples R China Renmin Univ China Sch Informat Beijing 100056 Peoples R China

Neural networks (NNs) have been widely adopted in various application domains. Deeper NNs greatly enhance the output accuracy, but complex NNs with more parameters incur intensive memory accesses, and the data usually need to be partitioned since it may exceed the on-chip storage. However, there is no research considering the partition and scheduling co-design of the NNs. In this paper, we propose a sparse NN data partition and loop scheduling scheme. We establish the compression efficiency model of the matrix sparse algorithm and design a partition selection method based on sparsity characteristics analyzed by the compression efficiency model. Further, we design a loop scheduling scheme based on the proper partition size. The experiment results show that the average memory access of each layer can be compressed to 68% of the original, and the throughput of the AlexNet, VGG and VGG19 is increased to an average of 1.66 times.

关键词： Sparse matrices Neural networks Partitioning algorithms Data models Optimization scheduling Sparse matrix neural networks loop scheduling compression partition

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Dynamic and Leakage Energy Minimization With Soft Real-Time loop scheduling and Voltage Assignment

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2010年第3期18卷 501-504页

作者： Qiu, Meikang Yang, Laurence T. Shao, Zili Sha, Edwin H. -M. Univ New Orleans Dept Elect & Comp Engn New Orleans LA 70148 USA St Francis Xavier Univ Dept Comp Sci Antigonish NS B2G 2W5 Canada Hong Kong Polytech Univ Dept Comp Kowloon Hong Kong Peoples R China Univ Texas Dallas Dept Comp Sci Richardson TX 75083 USA

With the shrinking of technology feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Traditional dynamic voltage scaling (DVS) fails to accurately address the impact of scaling on system power consumption as the leakage power increases exponentially. The combination of DVS and adaptive body biasing (ABB) is an effective technique to jointly optimize dynamic and leakage energy dissipation. In this paper, we propose an optimal soft real-time loop scheduling and voltage assignment algorithm, loop scheduling and voltage assignment to minimize energy, to minimize both dynamic and leakage energy via DVS and ABB. Voltage transition overhead has been considered in our approach. We conduct simulations on a set of digital signal processor benchmarks based on the power model of 70 nm technology. The simulation results show that our approach achieves significant energy saving compared to that of the integer linear programming approach.

关键词： Assignment dynamic voltage scaling (DVS) leakage power loop scheduling real-time

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Data dependent loop scheduling based on genetic algorithms for distributed and shared memory systems

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2004年第5期64卷 578-590页

作者： Aguilar, JL Leiss, EL Univ Los Andes Fac Ingn Dept Computat CEMISID Merida 5101 Venezuela Univ Houston Dept Comp Sci Houston TX 77204 USA

Many approaches have been described for the parallel loop scheduling problem for shared-memory systems, but little work has been done on the data-dependent loop scheduling problem (nested loops with loop carried dependencies). In this paper, we propose a general model for the data-dependent loop scheduling problem on distributed as well as shared memory systems. In order to achieve load balancing and low runtime scheduling and communication overhead, our model is based on a loop task graph and the notion of critical path. In addition, we develop a heuristic algorithm based on our model and on genetic algorithms to test the reliability of the model. We test our approach on different scenarios and benchmarks. The results are very encouraging and suggest a future parallel compiler implementation based on our model. (C) 2004 Elsevier Inc. All rights reserved.

关键词： loop scheduling loop-carried dependence parallel algorithms genetic algorithms performance optimization

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Design methodology for workload-aware loop scheduling strategies based on genetic algorithm and simulation

Design methodology for workload-aware loop scheduling strate...

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12th International Workshop on Java Technologies for Real-Time and Embedded Systems (JTRES)

作者： Penna, Pedro H. Castro, Marcio Freitas, Henrique C. Broquedis, Francois Mehaut, Jean-Francois Univ Fed Santa Catarina Dept Informat & Stat Florianopolis SC Brazil Pontificia Univ Catolica Minas Gerais PUC Minas Dept Comp Sci Belo Horizonte MG Brazil UGA INRIA CNRS Grenoble INP Grenoble France

In high-performance computing, the application's workload must be evenly balanced among threads to deliver cutting-edge performance and scalability. In OpenMP, the load balancing problem arises when scheduling loop iterations to threads. In this context, several scheduling strategies have been proposed, but they do not take into account the input workload of the application and thus turn out to be suboptimal. In this work, we introduce a design methodology to propose, study, and assess the performance of workload-aware loop scheduling strategies. In this methodology, a genetic algorithm is employed to explore the state space solution of the problem itself and to guide the design of new loop scheduling strategies, and a simulator is used to evaluate their performance. As a proof of concept, we show how the proposed methodology was used to propose and study a new workload-aware loop scheduling strategy named smart round-robin (SRR). We implemented this strategy into GNU Compiler Collection's OpenMP runtime. We carry out several experiments to validate the simulator and to evaluate the performance of SRR. Our experimental results show that SRR may deliver up to 37.89% and 14.10% better performance than OpenMP's dynamic loop scheduling strategy in the simulated environment and in a real-world application kernel, respectively. Copyright (c) 2016 John Wiley & Sons, Ltd.

关键词： loop scheduling workload-aware loop scheduler simulation genetic algorithm

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