It is critical to lower the power consumption of battery powered nodes in Internet-of-Things (IoT) applications while maintaining a high transmission throughput. In this article, a novel turbo coded lightweight rate c...
详细信息
It is critical to lower the power consumption of battery powered nodes in Internet-of-Things (IoT) applications while maintaining a high transmission throughput. In this article, a novel turbo coded lightweight rate compatible modulation (TLRCM) with a simple weight set {+/- 1} is proposed for IoT uplink transmission. Unlike narrowband IoT (NB-IoT) standard where the whole data block will be retransmitted repeatedly until the data are recovered successfully, the proposed TLRCM works in a rateless manner and can achieve a smooth rate adaptation to channel variations, reducing the number of symbols to be retransmitted. Thus, TLRCM can significantly reduce the power consumption of IoT device and improve transmission throughput. To reduce computational complexity, a 1-b subtraction and memory reading algorithm, which can be easily implemented in limited computing capability IoT devices, is proposed for the generation of TLRCM symbols. In addition, an iterative algorithm with significantly reduced complexity is proposed for TLRCM demodulation. Moreover, the reliable soft information from the output of TLRCM demodulator enables a fast convergence of Turbo codes decoding. The simulation results show that compared with the repetition transmission scheme in NB-IoT standard, the proposed TLRCM can reduce by over 37% the average transmission power consumption while maintaining a high throughput of transmission in both Gaussian channels and fading channels. The uniqueness of low-power consumption, high throughput transmission, and low-complexityimplementation enables the proposed TLRCM to be a potential technique for IoT applications.
This paper manages the equipment usage of the as of late presented Probabilistic Gradient-Descent Bit Flipping (PGDBF) decoder. The PGDBF is another kind of hard-choice decoder for low-Density Parity-Check (LDPC) code...
详细信息
This paper manages the equipment usage of the as of late presented Probabilistic Gradient-Descent Bit Flipping (PGDBF) decoder. The PGDBF is another kind of hard-choice decoder for low-Density Parity-Check (LDPC) code, with enhanced blunder adjustment execution because of the presentation of think arbitrary annoyance in the figuring units. In the PGDBF, the irregular bother works amid the bit-flipping venture, with the target to maintain a strategic distance from the fascination of alleged catching arrangements of the LDPC code. In this paper, we propose a capable mechanical assembly organizing which limits the favorable position overhead expected to execute the sporadic aggravations of the PGDBF. Our organizing relies on the usage of a Short Random Sequence (SRS) that is imitated to completely apply the PGDBF loosening up standards, and on an improvement of the most mind boggling pioneer unit.
Probabilistic gradient descent bit-flipping (PGDBF) is a hard-decision decoder for low-density parity-check (LDPC) codes, which offers a significant improvement in error correction, approaching the performance of soft...
详细信息
Probabilistic gradient descent bit-flipping (PGDBF) is a hard-decision decoder for low-density parity-check (LDPC) codes, which offers a significant improvement in error correction, approaching the performance of soft-information decoders on the binary symmetric channel. However, this outstanding performance is known to come with an augmentation of the decoder complexity, compared to the non-probabilistic gradient descent bit flipping (GDBF), becoming a drawback of this decoder. This paper presents a new approach to implementing PGDBF decoding for quasi-cyclic LDPC (QC-LDPC) codes, based on the so-called variable-node-shift architecture (VNSA). In VNSA-based PGDBF implementations, the regularity of QC-LDPC connection networks is used to cyclically shift the memory of the decoder, leading to the fact that, a variable node (VN) is processed by different computing units during the decoding process. With this modification, the probabilistic effects in VN operations can be produced by implementing different types of processing units, without requirement of a probabilistic signal generator. The VNSA is shown to further improve the decoding performance of the PGDBF, with respect to other hardware implementations reported in the literature, while reducing the complexity below that of the GDBF. The efficiency of the VNSA is proven by ASIC synthesis results and by decoding simulations.
The Gallager B (GaB), among the hard-decision class of low-density-parity-check (LDPC) algorithms, is an ideal candidate for designing high-throughput decoder hardware. However, GaB suffers from poor error-correction ...
详细信息
The Gallager B (GaB), among the hard-decision class of low-density-parity-check (LDPC) algorithms, is an ideal candidate for designing high-throughput decoder hardware. However, GaB suffers from poor error-correction performance. We introduce a probabilistic GaB (PGaB) algorithm that disturbs the decisions made during the decoding iterations randomly with a probability value determined based on experimental studies. We propose a heuristic that switches the decoding from GaB to PGaB after certain number of iterations and show that our heuristic reduces the average iteration count by up to 62% compared with GaB. We evaluate the hardware performance and resource requirement trends of PGaB over three quasicyclic codes using the Xilinx Virtex-6 field programmable gate array. We extend this analysis to performance comparison over our implementations of gradient descent bit flipping (GDBF) and probabilistic GDBF (PGDBF) algorithms for each code studied in this paper. We achieve up to four orders of magnitude better error correction performance than the GaB with less than 1% loss in throughput performance. Our heuristic consistently results with an improvement in maximum operational clock rate across all codes compared with the GDBF and PGDBF.
This paper deals with the hardware implementation of the recently introduced Probabilistic Gradient-Descent Bit-Flipping (PGDBF) decoder. The PGDBF is a new type of hard-decision decoder for low-Density Parity-Check (...
详细信息
This paper deals with the hardware implementation of the recently introduced Probabilistic Gradient-Descent Bit-Flipping (PGDBF) decoder. The PGDBF is a new type of hard-decision decoder for low-Density Parity-Check (LDPC) code, with improved error correction performance thanks to the introduction of deliberate random perturbation in the computing units. In the PGDBF, the random perturbation operates during the bit-flipping step, with the objective to avoid the attraction of so-called trapping-sets of the LDPC code. In this paper, we propose an efficient hardware architecture which minimizes the resource overhead needed to implement the random perturbations of the PGDBF. Our architecture is based on the use of a Short Random Sequence (SRS) that is duplicated to fully apply the PGDBF decoding rules, and on an optimization of the maximum finder unit. The generation of good SRS is crucial to maintain the outstanding decoding performance of PGDBF, and we propose two different methods with equivalent hardware overheads, but with different behaviors on different LDPC codes. Our designs show that the improved PGDBF performance gains can be obtained with a very small additional complexity, therefore providing a competitive hard-decision LDPC decoding solution for current standards.
In satellite navigation, the key to high precision is to make use of the carrier-phase measurements. The periodicity of the carrier-phase, however, leads to integer ambiguities. Often, resolving the full set of ambigu...
详细信息
In satellite navigation, the key to high precision is to make use of the carrier-phase measurements. The periodicity of the carrier-phase, however, leads to integer ambiguities. Often, resolving the full set of ambiguities cannot be accomplished for a given reliability constraint. In that case, it can be useful to resolve a subset of ambiguities. The selection of the subset should be based not only on the stochastic system model but also on the actual measurements from the tracking loops. This paper presents a solution to the problem of joint subset selection and ambiguity resolution. The proposed method can be interpreted as a generalized version of the class of integer aperture estimators. Two specific realizations of this new class of estimators are presented, based on different acceptance tests. Their computation requires only a single tree search, and can be efficiently implemented, e.g., in the framework of the well-known LAMBDA method. Numerical simulations with double difference measurements based on Galileo E1 signals are used to evaluate the performance of the introduced estimation schemes under a given reliability constraint. The results show a clear gain of partial fixing in terms of the probability of correct ambiguity resolution, leading to improved baseline estimates.
The rapid traffic growth and ubiquitous access requirements make it essential to explore the next generation (5G) wireless communication networks. In the current 5G research area, non-orthogonal multiple access has be...
详细信息
ISBN:
(纸本)9781479935123
The rapid traffic growth and ubiquitous access requirements make it essential to explore the next generation (5G) wireless communication networks. In the current 5G research area, non-orthogonal multiple access has been proposed as a paradigm shift of physical layer technologies. Among all the existing non-orthogonal technologies, the recently proposed sparse code multiple access (SCMA) scheme is shown to achieve a better link level performance. In this paper, we extend the study by proposing an unified framework to analyze the energy efficiency of SCMA scheme and a lowcomplexity decoding algorithm which is critical for prototyping. We show through simulation and prototype measurement results that SCMA scheme provides extra multiple access capability with reasonable complexity and energy consumption, and hence, can be regarded as an energy efficient approach for 5G wireless communication systems.
The rapid traffic growth and ubiquitous access requirements make it essential to explore the next generation (5G) wireless communication networks. In the current 5G research area, non-orthogonal multiple access has be...
详细信息
ISBN:
(纸本)9781479935130
The rapid traffic growth and ubiquitous access requirements make it essential to explore the next generation (5G) wireless communication networks. In the current 5G research area, non-orthogonal multiple access has been proposed as a paradigm shift of physical layer technologies. Among all the existing non-orthogonal technologies, the recently proposed sparse code multiple access (SCMA) scheme is shown to achieve a better link level performance. In this paper, we extend the study by proposing an unified framework to analyze the energy efficiency of SCMA scheme and a lowcomplexity decoding algorithm which is critical for prototyping. We show through simulation and prototype measurement results that SCMA scheme provides extra multiple access capability with reasonable complexity and energy consumption, and hence, can be regarded as an energy efficient approach for 5G wireless communication systems.
Similar to the orthogonal frequency division multiple access (OFDMA) system, the single-carrier frequency division multiple access (SC-FDMA) system also suffers from frequency mismatches between the transmitter and th...
详细信息
Similar to the orthogonal frequency division multiple access (OFDMA) system, the single-carrier frequency division multiple access (SC-FDMA) system also suffers from frequency mismatches between the transmitter and the receiver. As a result, in this system, the carrier frequency offsets (CFOs) disrupt the orthogonality between subcarriers and give rise to inter-carrier interference (ICI) and multiple access interference (MAI) among users. The authors present a new minimum mean square error (MMSE) equaliser, which jointly performs equalisation and carrier frequency offsets (CFOs) compensation. The mathematical expression of this equaliser has been derived taking into account the MAI and the channel noise. A low complexity implementation of the proposed equalisation scheme using a banded matrix approximation is presented here. From the obtained simulation results, the proposed equalisation scheme is able to enhance the performance of the SC-FDMA system, even in the presence of estimation errors.
The paper proposes a low-complexityimplementation of the Vector Delay Lock Loop (VDLL) suitable for low-cost receivers operating with several GNSS constellations in indoor and urban scenarios. The tracking algorithm ...
详细信息
ISBN:
(纸本)9781424487417
The paper proposes a low-complexityimplementation of the Vector Delay Lock Loop (VDLL) suitable for low-cost receivers operating with several GNSS constellations in indoor and urban scenarios. The tracking algorithm is based on the propagation of the estimated space/time trajectory through a grid of cells in two steps: prediction and updating. Side information about the receiver's motion and/or environment can be easily incorporated by assigning different a priori probabilities to the cells in the prediction step. The algorithm can operate reliably with a large range of satellites and has shown a remarkable robustness to the multipath effect, especially when the number of satellites in view is high.
暂无评论