low-densityparity-check (LDPC) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study lowcomplexitysoft-input, soft-output (SISO)...
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low-densityparity-check (LDPC) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study lowcomplexitysoft-input, soft-output (SISO) field programmable gate arrays (FPGA) implementations of a novel logarithmic sum-product (LogSP) iterative LDPC decoder and a recently proposed simplified soft Euclidean distance (SSD) iterative LDPC decoder are presented, and their complexities and performance are compared. These implementations operate over any choice of paritycheck matrix (including those randomly generated, structurally generated and either systematic or non-systematic) and can be parametrically adapted for any code rate. The proposed implementations are both of very lowcomplexity, because they operate using only sums, subtractions, comparisons and look-up tables, which makes them particularly suitable for FPGA realisation. The SSD decoder has a lower implementation complexity than the LogSP LDPC decoder and it also offers the advantage of not requiring knowledge of the channel signal-to-noise ratio, unlike most other LDPC decoders.
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