This paper presents an architectural-space exploration methodology for designing approximate multipliers. Unlike state-of-the-art, our methodology generates various design points by adapting three key parameters: (1) ...
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ISBN:
(纸本)9781450344661
This paper presents an architectural-space exploration methodology for designing approximate multipliers. Unlike state-of-the-art, our methodology generates various design points by adapting three key parameters: (1) different types of elementary approximate multiply modules, (2) different types of elementary adder modules for summing the partial products, and (3) selection of bits for approximation in a wide-bit multiplier design. Generation and exploration of such a design space enables a wide-range of multipliers with varying approximation levels, each exhibiting distinct area, power, and output quality, and thereby facilitates approximate computing at higher abstraction levels. We synthesized our designs using Synopsys Design Compiler with a TSMC 45nm technology library and verified using ModelSim gate-level simulations. power and quality evaluations for various designs are performed using PrimeTime and behavioral models, respectively. The selected designs are then deployed in a JPEG application. For reproducibility and to facilitate further research and development at higher abstraction layers, we have released the RTL and behavioral models of these approximate multipliers and adders as an open-source library at https://***/projects/lpaclib/.
We propose a novel power-constrained RGB-to-RGBW conversion algorithm for emissive RGBW displays. We measure the perceived color distortion using a color difference model in a perceptually uniform color space, and com...
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ISBN:
(纸本)9781479928934
We propose a novel power-constrained RGB-to-RGBW conversion algorithm for emissive RGBW displays. We measure the perceived color distortion using a color difference model in a perceptually uniform color space, and compute the power consumption for displaying an RGBW pixel on an emissive display. The main contribution is to formulate the optimization problem to minimize the color distortion subject to the constraint on the power consumption. Then, we solve it efficiently to convert an image in real time. Simulation results show that the proposed algorithm provides significantly less color distortion than the conventional methods while providing a graceful trade-off with the amount of power consumed.
A new approach to an analog ultra-lowpower medium-resolution vision chip design is presented. The prototype chip performs low-level imageprocessing algorithms in real time. Only a photo-diode, MOS switches and two c...
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A new approach to an analog ultra-lowpower medium-resolution vision chip design is presented. The prototype chip performs low-level imageprocessing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3 x 3 kernel. The proof-of-concept circuit is implemented in 0.35 mu m CMOS technology, and contains a 64 x 64 SIMD matrix with embedded APEs. The matrix dissipates less than 0.3 mW (less than 0.1 mu W per APE) of power under 3.3 V supply, and its imageprocessing speed is up to 100 frames/s.
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