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low-complexity implementation of quasi-OBE algorithm

ELECTRONICS LETTERS 2012年第11期48卷 621-623页

作者： Arablouei, R. Dogancay, K. Univ S Australia Inst Telecommun Res Mawson Lakes SA Australia

The quasi-OBE (QOBE) algorithm is a set-membership adaptive filtering algorithm based on the principles of optimal bounding ellipsoid (OBE) processing. This algorithm can provide enhanced convergence and tracking performance as well as reduced average computational complexity in comparison with the more traditional adaptive filtering algorithms. In this reported work, the QOBE algorithm is implemented using the dichotomous coordinate descent iterations. This significantly reduces QOBE's per-update computational complexity, especially the number of required multiplications, and delivers a trade-off between performance and complexity.

关键词： quasiOBE algorithm low-complexity implementation tracking performance Filtering methods in signal processing iterative methods OBE processing adaptive filters dichotomous coordinate descent iterations Interpolation and function approximation (numerical analysis) set-membership adaptive filtering algorithm Signal processing theory computational complexity QOBE algorithm optimal bounding ellipsoid processing

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A new discrete wavelet transform appropriate for hardware implementation

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2020年第3期48卷 369-384页

作者： Meshkat, Amin Dehghani, Rasoul Isfahan Univ Technol Dept Elect & Comp Engn Esfahan Iran

A new method for computation of discrete wavelet transform is introduced. The impulse response of the finite impulse response (FIR) filter, as the main block in filter bank method, is realized such that orthonormal wavelet transform is achieved without using any multiplier as the most challenging part of the FIR filters. It is proved that the calculated Sobolev regularity of the proposed wavelet is higher than that of Daubechies for the same support width. Compared with most popular known wavelets, simulation results of the newly introduced wavelet for signal denoising prove remarkable advantage of our wavelet especially in terms of complexity and power consumption. The proposed wavelet and well-known Daubechies wavelet are separately implemented on the Spartan-6 FPGA (Field Programmable Gate Array) to compare the performance of them. The occupied slices and LUTs (Lookup Table) in realization of the proposed wavelet in comparison with those of Daubechies wavelet are decreased by 50% and 56%, respectively. Its power consumption at 100 MHz is also reduced by 86% in comparison with the Daubechies wavelet, and maximum frequency is increased by 186%. implementation with standard cells of a 0.18-mu m CMOS (Complementary Metal Oxide Semiconductor Field Effect Transistor) technology shows 75% and 85% reduction in the power and chip area, respectively.

关键词： discrete wavelet transforms low-complexity implementation low-power denoising Sobolev regularity

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Beam Structured Channel Estimation for HF Skywave Massive MIMO-OFDM Communications

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IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS 2024年第11期23卷 16301-16315页

作者： Shi, Ding Song, Linfeng Gao, Xiqi Wang, Jiaheng Bengtsson, Mats Li, Geoffrey Ye Xia, Xiang-Gen Southeast Univ Natl Mobile Commun Res Lab Nanjing 210096 Peoples R China Purple Mt Labs Nanjing 211111 Peoples R China KTH Royal Inst Technol Sch Elect Engn & Comp Sci S-10044 Stockholm Sweden Imperial Coll London Dept Elect & Elect Engn London SW7 2AZ England Univ Delaware Dept Elect & Comp Engn Newark DE 19716 USA

In this paper, we investigate high frequency (HF) skywave massive multiple-input multiple-output (MIMO) communications with orthogonal frequency division multiplexing (OFDM) modulation. Based on the triple-beam (TB) based channel model and the channel sparsity in the TB domain, we propose a beam structured channel estimation (BSCE) approach. Specifically, we show that the space-frequency-time (SFT) domain estimator design for each TB domain channel element can be transformed into that of a low-dimensional TB domain estimator and the resulting SFT domain estimator is beam structured. We also present a method to select the TBs used for BSCE. Then we generalize the proposed BSCE by introducing window functions and a turbo principle to achieve a superior trade-off between complexity and performance. Furthermore, we present a low-complexity design and implementation of BSCE by exploiting the characteristics of the TB matrix. Simulation results validate the proposed theory and methods.

关键词： Channel estimation Massive MIMO OFDM Channel models Estimation Vectors Time-frequency analysis Massive MIMO-OFDM HF skywave communications beam structured channel estimation low-complexity implementation

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Design. of multiplierless correlators for timing synchronization in IEEE 802.11a wireless LANs

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2003年第1期49卷 107-114页

作者： Yip, KW Wu, YC Ng, TS Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China

Timing synchronization for IEEE 802.11a WLANs requires using a correlator to correlate the received signal with a known waveform. Straightforward implementation of this correlator results in the need to perform 320 million complex multiplications per second. This significant requirement can be eliminated by using, multiplierless correlators. In this paper, multiplierless correlators are designed based on constraining the real and imaginary parts of correlator coefficients to be sums of, powers of two. Sets of coefficients that yield good synchronization performance for simple AWGN channels are first identified;then their goodness for indoor communication environments is verified by simulation for multipath fading channels. Several multiplierless correlators are found. Comparison among these correlators identifies a good one that requires to perform only 26 addition/subtraction operations per correlator output while a similar synchronization performance can be maintained.(1).

关键词： low-complexity implementation multiplierless correlator timing synchronization wireless local area network

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Fine-Grained Bit-Flipping Decoding for LDPC Codes

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2020年第5期67卷 896-900页

作者： Chen, Yuxing Cui, Hangxuan Lin, Jun Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210008 Peoples R China

This brief presents a novel class of hard-decision algorithms for decoding low density parity check codes. The new algorithms, named fine-grained bit-flipping (FBF) algorithms, employ a detailed classification of each bit, by introducing the XOR value of its estimated and received value as a subdividing criterion. The fine-grained classification allows the algorithms to strengthen the information utilization during each iteration. Simulation results show that the FBF algorithms can achieve up to 5 times better decoding performance than the state-of-the-art bit-flipping algorithms over the binary symmetric channel. Additionally, a well-optimized hardware architecture is developed for implementing FBF algorithms. Compared to other decoders, implementation results demonstrate that the FBF decoders achieve higher throughput and area efficiency.

关键词： low density parity check codes fine-grained classification bit-flipping high throughput low-complexity implementation

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Pseudo-random Gaussian distribution through optimised LFSR permutations

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ELECTRONICS LETTERS 2015年第25期51卷 2099-2100页

作者： Condo, C. Gross, W. J. McGill Univ Elect & Comp Engn Montreal PQ Canada

Efficient hardware solutions to generate Gaussian-distributed random numbers are required in many applications. Linear feedback shift registers ( LFSRs) are a low-complexity implementation of an approximated uniform pseudo-random distribution: multiple LFSRs can be used in combination to approximate a Gaussian distribution with a low complexity cost. The technique proposed in this work exploits the same principle but relies on a single LFSR and ad-hoc permutations of its bits to obtain an accurate approximation of a Gaussian distribution with low maximum autocorrelation, leading to a very low complexity implementation of a Gaussian pseudo-random number generator.

关键词： maximum autocorrelation Digital arithmetic methods LFSR linear feedback shift registers optimised LFSR permutations Gaussian pseudorandom number generator low-complexity implementation complexity cost Logic circuits pseudorandom Gaussian distribution approximation Logic and switching circuits shift registers Other topics in statistics random number generation Gaussian-distributed random numbers circuit complexity Computational complexity ad-hoc permutations Gaussian distribution approximated uniform pseudorandom distribution

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Recursive all-lag reference-code correlators

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2000年第12期47卷 1542-1547页

作者： Ng, TS Yip, KW Cheng, CL Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China

An all-lag reference-code correlator generates an all-lag even-or odd-correlation vector at a rate equal to the rate of incoming data samples. Direct implementation of an all-lag reference-code correlator requires N parallel correlators, and the resultant degree of complexity is of the order N-2, where N is the length of the reference code. This paper derives two recursive forms for all-lag reference-code correlators. One generates all-lag even correlation and the other one generates all-lag odd correlation. It is shown that the proposed recursive all-lag reference-code correlator can be implemented with a complexity approximately equal to that of a single parallel correlator. That is, the degree of complexity of the proposed recursive all-lag reference-code correlator is of the order N. Thus, substantial reduction in the implementation complexity is achieved.

关键词： all-lag reference-code correlator bank of serial correlators low-complexity implementation parallel correlator recursive relationship serial correlator spread spectrum

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A Probabilistic Parallel Bit-Flipping Decoder for low-Density Parity-Check Codes

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2019年第1期66卷 403-416页

作者： Le, Khoa Ghaffari, Fakhreddine Kessal, Lounis Declercq, David Boutillon, Emmanuel Winstead, Chris Vasic, Bane Univ Cergy Pontoise Univ Paris Sein ENSEA ETISUMR8051CNRS F-95014 Cergy Pontoise France Univ Bretagne Sud UMR 6285 Lab STICC F-56321 Lorient France Utah State Univ Dept Elect & Comp Engn Logan UT 84322 USA Univ Arizona Dept Elect & Comp Engn Tucson AZ 85719 USA

This paper presents a new bit flipping (BF) decoder, called the probabilistic parallel BF (PPBF) for low-density parity-check codes on the binary symmetric channel. In the PPBF, the flipping operation is performed in a probabilistic manner which is shown to significantly improve the error correction performance. The advantage of the PPBF also comes from the fact that no global computation is required during the decoding process and that all the computations can be executed in the local computing units and in parallel. The PPBF provides a considerable improvement of the operating frequency and complexity, compared to other known BF decoders, while obtaining a significant gain in error correction. An improved version of the PPBF, called non-syndrome PPBF is also introduced, in which the global syndrome check is moved out of the critical path and a new terminating mechanism is proposed. In order to show the superiority of the new decoders in terms of hardware efficiency and decoding throughput, the corresponding hardware architectures are presented in Section II. The application-specific integrated circuit synthesis results confirm that the operating frequency of the proposed decoders is significantly improved, compared to that of the BF decoders in the literature while requiring lower complexity to be efficiently implemented.

关键词： low-density parity-check codes iterative decoding probabilistic bit flipping decoding high decoding throughput low-complexity implementation

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High Performance LDPC Decoder design using FPGA 9

High Performance LDPC Decoder design using FPGA

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9th International Conference on Emerging Trends in Engineering and Technology - Signal and Information Processing (ICETET-SIP)

作者： Pawankar, Shraddha Mohota, Nilesh JD Coll Engn & Management Nagpur Maharashtra India JD Coll Engn & Management Dept Elect Nagpur Maharashtra India

ISBN: (纸本)9781728135069

LDPC codes are an important aspect of 5G communication systems. This paper presents high performance design of low-density parity-check decoder on reconfigurable FPGA. LDPC codes are one of the most efficient error correcting codes for implementation on FPGA. The main aim is to implement a low complexity architecture of the LDPC decoder on the FPGA (Field Programmable Gate Array). The two main components of LDPC are VNU and CNU. Our efficient decoding structure will reduce the complexity with the help of check node unit (CNU) and the variable node unit (VNU) using min-sum algorithm for getting fewer slice resources. Here, we have used multiplexed storage structure for storing nod message to get the result in minimum FPGA resources. LDPC is quite an integral part in deep space communications and its potential utilization in the area which is highly explored. In space data systems it is quite important to have a LDPC decoder which has both low complexity and high performance architecture. Therefore the low-complexity method becomes an efficient method to achieve the requirements put in future by many wired and wireless communication system.

关键词： LDPC decoder low-complexity implementation Min-Sum algorithm

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low-complexity Acoustic Scene Classification Using Data Generation Based On Primary Ambient Extraction 16

Low-Complexity Acoustic Scene Classification Using Data Gene...

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16th IEEE International Symposium on Broadband Multimedia Systems and Broadcasting (IEEE BMSB)

作者： Shi, Chuang Yang, Haocong Liu, Yingzi Liang, Jiangnan Univ Elect Sci & Technol China Sch Informat & Commun Engn Chengdu Peoples R China

ISBN: (纸本)9781665449083

Acoustic scene classification (ASC) is an important branch of machine hearing. Since ASC systems are intended to be deployed on mobile devices, how to ensure the performance under low-complexity implementation has become an attracting research problem. The state-of-the-art methods include compressing parameter precisions, reducing quantization bits, introducing sparsity constraints and so on. These methods mainly focus on the model level optimization, while explorations are rarely originated from the data level. This paper introduces a train of thoughts from data level, inspired by a stereo audio processing algorithm, namely the primary ambient extraction (PAE), which generates additional samples through audio up-mixing. The experiment results demonstrate that the proposed method exhibits better performance than a group of ASC baseline systems without data level optimization, not to mention that the proposed method is compatible with the existing model level optimization.

关键词： Acoustic scene classification low-complexity implementation convolutional neural network primary ambient extraction

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