LDPC codes are an important aspect of 5G communication systems. This paper presents high performance design of low-density parity-check decoder on reconfigurable FPGA. LDPC codes are one of the most efficient error co...
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ISBN:
(纸本)9781728135069
LDPC codes are an important aspect of 5G communication systems. This paper presents high performance design of low-density parity-check decoder on reconfigurable FPGA. LDPC codes are one of the most efficient error correcting codes for implementation on FPGA. The main aim is to implement a lowcomplexity architecture of the LDPC decoder on the FPGA (Field Programmable Gate Array). The two main components of LDPC are VNU and CNU. Our efficient decoding structure will reduce the complexity with the help of check node unit (CNU) and the variable node unit (VNU) using min-sum algorithm for getting fewer slice resources. Here, we have used multiplexed storage structure for storing nod message to get the result in minimum FPGA resources. LDPC is quite an integral part in deep space communications and its potential utilization in the area which is highly explored. In space data systems it is quite important to have a LDPC decoder which has both lowcomplexity and high performance architecture. Therefore the low-complexity method becomes an efficient method to achieve the requirements put in future by many wired and wireless communication system.
This paper presents an efficient multiplierless timing synchronization algorithm for OFDM symbols in WLANs following 802.11x protocols which requires using numerous multipliers to correlate the received training seque...
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ISBN:
(纸本)9781479944194
This paper presents an efficient multiplierless timing synchronization algorithm for OFDM symbols in WLANs following 802.11x protocols which requires using numerous multipliers to correlate the received training sequence with local long training sequence in FH (frame header). The proposed algorithm approximates and quantifies the value of the long training sequence elements to the nearest value of integer power of 2 based on the IEEE 802.11x protocols, then the multiplication can be directly simplified as a shift operation in the correlator of symbol synchronization section. The presented algorithm doesn't need to incorporate any multiplication or addition when comparing with the existing algorithms. Besides, its implementationcomplexity is drastically reduced by merely utilizing the logic resources in FPGA. A simulation was carried out in the Simulink platform, and the results shows that the proposed algorithm performs almost the same as the traditional technique with multiply correlators. However, it performs much better at given low SNR than the existing multiplierless correlators algorithm.
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