A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decode...
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A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10-4 at 2.7 Eb/No (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.
In this study, an optimization model for offline scheduling policy of low-densityparity-check (LDPC) codes is proposed to improve the decoding efficiency of the belief propagation (BP). The optimization model uses th...
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In this study, an optimization model for offline scheduling policy of low-densityparity-check (LDPC) codes is proposed to improve the decoding efficiency of the belief propagation (BP). The optimization model uses the number of messages passed (NMP) as a metric to evaluate complexity, and two metrics, average entropy (AE), and gap to maximum a posteriori (GAP), to evaluate BP decoding performance. Based on this model, an algorithm is proposed to optimize the scheduling sequence for reduced decoding complexity and superior performance compared to layered BP (LBP). We validated the proposed algorithm on LDPC codes constructed following 5G New Radio, which resulted in a reduction of decoding complexity of more than 20% compared to LBP.
In this paper we analyse the performance of quantum low-densityparity-check (LDPC) codes over quantum memory channels for correcting correlated errors, where the quantum LDPC codes we use are the hypergraph product q...
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In this paper we analyse the performance of quantum low-densityparity-check (LDPC) codes over quantum memory channels for correcting correlated errors, where the quantum LDPC codes we use are the hypergraph product quantum LDPC codes. We generalize the classical Gilbert-Elliot markovian memory channel to the quantum Gilbert-Elliot channel and use it to model the memory effect in quantum memory channels. The simulation results show the memory effects in quantum GE channels has a bad effect to the performance of hypergraph product quantum LDPC codes. Then we propose a concatenation scheme by serially concatenating two hypergraph product quantum LDPC codes and it is shown that the serial concatenation scheme can improve the performance of hypergraph product quantum LDPC codes and lower down the error floor over quantum GE channels.
Increasing the reconciliation efficiency and decreasing the frame error rate (FER) during the reconciliation for continuous-variable quantum key distribution (CV-QKD) can improve the secret key rate of CV-QKD. In this...
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Increasing the reconciliation efficiency and decreasing the frame error rate (FER) during the reconciliation for continuous-variable quantum key distribution (CV-QKD) can improve the secret key rate of CV-QKD. In this paper, we introduce matryoshka globally coupled low-densityparity-check (MGC-LDPC) codes with high error correction performance into CV-QKD to increase the reconciliation efficiency. To decrease the FER, we propose an optimization method for MGC-LDPC codes during the reconciliation, thus improving the secret key rate of CV-QKD. Simulation experiments show that the reconciliation efficiency of CV-QKD can be improved to 98.39% by using the optimized MGC-LDPC codes, and the secure transmission distance can be extended to 190 km.
For a two-variance model of the Flash read channel that degrades as a function of the number of program/erase cycles, this paper demonstrates that selecting write voltages to maximize the minimum page mutual informati...
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ISBN:
(纸本)9798350382853;9798350382846
For a two-variance model of the Flash read channel that degrades as a function of the number of program/erase cycles, this paper demonstrates that selecting write voltages to maximize the minimum page mutual information (MI) can increase device lifetime. In multi-level cell (MLC) Flash memory, one of four voltage levels is written to each cell, according to the values of the most-significant bit (MSB) page and the least-significant bit (LSB) page. In our model, each voltage level is then distorted by signal-dependent additive Gaussian noise that approximates the Flash read channel. When performing an initial read of a page in MLC flash, one (for LSB) or two (for MSB) bits of information are read for each cell of the page. If LDPC decoding fails after the initial read, then an enhanced-precision read is performed. This paper shows that jointly designing write voltage levels and read thresholds to maximize the minimum MI between a page and its associated initial or enhanced-precision read bits can improve LDPC decoding performance.
A new search method named two-dimensional greedy search (TDGS) is proposed to progressively determine each element within an exponent matrix, so as to generate quasi-cyclic (QC) low-densityparity-check (LDPC) codes w...
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ISBN:
(纸本)9798350348941;9798350348934
A new search method named two-dimensional greedy search (TDGS) is proposed to progressively determine each element within an exponent matrix, so as to generate quasi-cyclic (QC) low-densityparity-check (LDPC) codes without 4-cycles and 6-cycles. By applying four different two-dimensional scanning orders to the TDGS, a design framework is formulated to unify several existing and novel explicit constructions for short (3, L)-regular QC-LDPC codes without 4-cycles and 6-cycles. Through equivalence analysis between the exponent matrices greedily found by the TDGS and directly defined by explicit constructions, novel girth properties of (and connections between) these existing explicit constructions are also revealed.
low-densityparity-check (LDPC) codes are widely used in communication systems for their high error-correcting performance. This survey introduces the elements of LDPC codes: decoding algorithms, code construction, en...
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low-densityparity-check (LDPC) codes are widely used in communication systems for their high error-correcting performance. This survey introduces the elements of LDPC codes: decoding algorithms, code construction, encoding algorithms, and several classes of LDPC codes.
low-densityparity-check (LDPC) code is a type of forward error-correction code with excellent performance, and has been widely used in many modern communication standards. The second-generation satellite broadcasting...
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low-densityparity-check (LDPC) code is a type of forward error-correction code with excellent performance, and has been widely used in many modern communication standards. The second-generation satellite broadcasting standard (DVB-S2) and its extension (DVB-S2X) adopt a special Irregular Repeated Accumulate (IRA) LDPC code as inner coding scheme. However, due to the large block size, most of the architectures proposed so far use Random Access Memory (RAM) to store and update the encoding results, and the delay caused by address-controlled read and write operations and barrel shift during computation inevitably limits the upper bound of encoder throughput. In this paper, by extracting the periodicity of the parity-check matrix, we introduce a fast encoding algorithm that can efficiently process the multiplication of the information sequence and a large-dimensional sparse matrix, and propose an encoder architecture with low encoding delay and high throughput. The proposed architecture has been implemented and tested on a Xilinx Kintex-7 FPGA, and the result show that the encoder architecture can achieve the highest throughput of 47.5 Gbps at a clock frequency of 280 MHz.
In this paper,a new type of edge coloring of graphs together with an algorithm for such an edge coloring is presented to construct some columnweight three low-densityparity-check(LDPC)codes whose Tanner graphs are fr...
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In this paper,a new type of edge coloring of graphs together with an algorithm for such an edge coloring is presented to construct some columnweight three low-densityparity-check(LDPC)codes whose Tanner graphs are free of *** kind of edge coloring is applied on some well-known classes of graphs such as complete graphs and complete bipartite graphs to generate some column-weight 3 LDPC codes having flexibility in terms of code length and ***,the constructed(3;k)-regular codes with regularities k=4;5;:::;22 have lengths n=12;20;26,35;48;57;70;88;104;117;140;155;176;204;228;247;280;301;330;having minimum block length compared to the best known similar codes in the *** addition to linear complexity of generating such parity-check matrices,they can be considered as the base matrices of some quasi-cyclic(QC)LDPC codes with maximum achievable girth 18,which inherit the low-complexity encoder implementations of QC-LDPC *** results show that the QC-LDPC codes with large girth lifted from the constructed base matrices have good performances and outperform random codes,progressive edge growth LDPC codes,some finite fields and group rings based QC-LDPC codes and also have a close competition to the standard IEEE 802.16e(WiMAX)code.
In this paper, we propose a robust parameters estimation algorithm for channel coded systems based on the low-densityparity-check (LDPC) code over fading channels with impulse noise. The estimated parameters are then...
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In this paper, we propose a robust parameters estimation algorithm for channel coded systems based on the low-densityparity-check (LDPC) code over fading channels with impulse noise. The estimated parameters are then used to generate bit log-likelihood ratios (LLRs) for a soft-inputLDPC decoder. The expectation-maximization (EM) algorithm is used to estimate the parameters, including the channel gain and the parameters of the Bernoulli-Gaussian (B-G) impulse noise model. The parameters can be estimated accurately and the average number of iterations of the proposed algorithm is acceptable. Simulation results show that over a wide range of impulse noise power, the proposed algorithm approaches the optimal performance under different Rician channel factors and even under Middleton class-A (M-CA) impulse noise models.
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