This paper is concerned with a class of product codes, referred to as CA-polar-SPC codes, where the cyclic redundancy check (CRC) aided polar (CA-polar) codes are column component codes and single parity-check (SPC) c...
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ISBN:
(纸本)9798350348941;9798350348934
This paper is concerned with a class of product codes, referred to as CA-polar-SPC codes, where the cyclic redundancy check (CRC) aided polar (CA-polar) codes are column component codes and single parity-check (SPC) codes are row component codes. With the help of SPCs, a decoding scheme is proposed to improve the performance of CA-polar codes at the expense of only a minor increase in decoding complexity and latency. Distinguished from the conventional iterative decoding of product codes, the proposed decoding outputs immediately the successfully decoded columns without waiting for the reception of the entire product block. Only those unsuccessfully decoded columns are further decoded with updated messages from the row decoder by treating the successfully decoded columns as determined messages instead of soft messages. Extensive simulation results show that the proposed CA-polar-SPC code outperforms the underlying CA-polar code over binary-input additive white Gaussian noise (Bi-AWGN) channels with only a minor increase in decodinglatency.
Bit flipping can be used as a postprocessing technique to further improve the performance for successive cancellation list (SCL) decoding of polar codes. However, the number of bit-flipping trials could increase the d...
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ISBN:
(纸本)9781538674628
Bit flipping can be used as a postprocessing technique to further improve the performance for successive cancellation list (SCL) decoding of polar codes. However, the number of bit-flipping trials could increase the decodinglatency significantly, which is not welcome in practice. In this paper, we propose a lowlatency SCL bit flipping decoding scheme, which is restricted to just single round of post-processing. The use of multiple votes for a more accurate estimation of path survival probability is proposed to locate the first error event of SCL decoding. Simulations show the sound improvement compared to the existing SCL bit-flipping decoding methods.
This paper proposes a decoding strategy for end-to-end simultaneous speech translation. We leverage end-to-end models trained in offline mode and conduct an empirical study for two language pairs (English-to-German an...
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ISBN:
(纸本)9781728176055
This paper proposes a decoding strategy for end-to-end simultaneous speech translation. We leverage end-to-end models trained in offline mode and conduct an empirical study for two language pairs (English-to-German and English-to-Portuguese). We also investigate different output token granularities including characters and Byte Pair Encoding (BPE) units. The results show that the proposed decoding approach allows to control BLEU/Average Lagging trade-off along different latency regimes. Our best decoding settings achieve comparable results with a strong cascade model evaluated on the simultaneous translation track of IWSLT 2020 shared task.
While long polar codes can achieve the capacity of arbitrary binary-input discrete memoryless channels when decoded by a low complexity successive-cancellation (SC) algorithm, the error performance of the SC algorithm...
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While long polar codes can achieve the capacity of arbitrary binary-input discrete memoryless channels when decoded by a low complexity successive-cancellation (SC) algorithm, the error performance of the SC algorithm is inferior for polar codes with finite block lengths. The cyclic redundancy check (CRC)-aided SC list (SCL) decoding algorithm has better error performance than the SC algorithm. However, current CRC-aided SCL decoders still suffer from long decodinglatency and limited throughput. In this paper, a reduced latency list decoding (RLLD) algorithm for polar codes is proposed. Our RLLD algorithm performs the list decoding on a binary tree, whose leaves correspond to the bits of a polar code. In existing SCL decoding algorithms, all the nodes in the tree are traversed, and all possibilities of the information bits are considered. Instead, our RLLD algorithm visits much fewer nodes in the tree and considers fewer possibilities of the information bits. When configured properly, our RLLD algorithm significantly reduces the decodinglatency and, hence, improves throughput, while introducing little performance degradation. Based on our RLLD algorithm, we also propose a high throughput list decoder architecture, which is suitable for larger block lengths due to its scalable partial sum computation unit. Our decoder architecture has been implemented for different block lengths and list sizes using the TSMC 90-nm CMOS technology. The implementation results demonstrate that our decoders achieve significant latency reduction and area efficiency improvement compared with the other list polar decoders in the literature.
In this paper, we present a novel scheduling method that reduces the latency of polar decoders significantly. Unlike the prior pruning-based successive cancellation list (SCL) decoding that suffers from a number of id...
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ISBN:
(纸本)9781728176055
In this paper, we present a novel scheduling method that reduces the latency of polar decoders significantly. Unlike the prior pruning-based successive cancellation list (SCL) decoding that suffers from a number of idle cycles, the proposed overlapped SCL scheme immediately begins node operations without waiting for the list to be sorted, being exempt from such unfavorable cycles. All possible candidates for the next node operations are precomputed in parallel with the pruning operations, and are readily selected to minimize the latency. For the 5G New Radio systems, the proposed method shortens the decodinglatency of the state-of-the-art approaches by up to 22% without degrading the error-correcting performance.
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