In the following a massive MIMO 5G < 6 GHz base station implementation is presented which is capable of real-time zero forcing precoding on a single central signal processing (CSP) FPGA. The built prototype is capa...
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ISBN:
(纸本)9781728154787
In the following a massive MIMO 5G < 6 GHz base station implementation is presented which is capable of real-time zero forcing precoding on a single central signal processing (CSP) FPGA. The built prototype is capable of simultaneously driving M = 196 separate RF ports all delivering samples to the CSP FPGA. Each RF chain's ADCs and DACs are running at 40 MSPS at full roll-out. The power consumption of the remote radio head is 1.56 W per RF port when running at a sample rate of 15.36 MSPS. The system allows for hardware-in-the-loop operation and real-time baseband signal processing with a round trip delay of 278 mu s when processing 64 antennas and 8 simultaneous user streams for an 5 GNR-like OFDMA system with 1024 sub-carriers and 50 resource blocks (600 used subcarriers) with a sample frequency of 15.36 MHz and a central signal processing clock of 184.32 MHz. The reciprocity calibration system runs completely internal to the system and doesn't radiate signals for the calibration procedure. Furthermore the central single-FPGA signal processing architecture allows for simplified implementation of algorithms and maintenance of the system.
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