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INTERNATIONAL JOURNAL OF EMERGING TECHNOLOGIES IN LEARNING 2019年第4期14卷 31-43页

作者： Yang Hong Zhou Xinyi Chengdu Normal Univ Chengdu Sichuan Peoples R China

In order to solve the problems of resource storage, resource delivery delay and other issues in the online learning process, it is studied and analyzed from the perspective of process goals. Firstly, a measurable e-learning process capability maturity model (EPCMM) is established. Then, based on the analysis of workflows in EPCMM's five process areas, a mapping relationship between major activities and key objectives is established in the process area. Finally, the mapping algorithm of online learning process features to process goals and the mapping algorithm of online learning metrics to process features are given. The practical results show that compared with the classical algorithm, this algorithm can effectively reduce the average transmission delay of online learning resources and improve the load balance of the system.

关键词： Online learning mapping algorithm process model

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An energy-aware online task mapping algorithm in NoC-based system

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JOURNAL OF SUPERCOMPUTING 2013年第3期64卷 1021-1037页

作者： Xie, Bin Chen, Tianzhou Hu, Wei Tang, Xingsheng Wang, Dazhou Zhejiang Univ Coll Comp Sci Hangzhou 310027 Zhejiang Peoples R China Wuhan Univ Sci & Technol Coll Comp Sci & Technol Wuhan 430065 Peoples R China

With the development of the semiconductor technology, more processors can be integrated onto a single chip. Network-on-Chip is an efficient communication solution for many-core system. However, enhancing performance with lower energy consumption is still a challenge. One critical issue is mapping applications to NoC. This work proposed an online mapping method, which optimizes task mapping algorithm to reduce communication energy consumption. The communication status of applications at runtime is analyzed first. Then, the algorithm computes the mapping placement dynamically and implements the real-time mapping online. Experimental results based on simulation show that the algorithm proposed in this article can achieve more than 20% communication energy saving compared with first fit mapping and nearest neighbor mapping. The migration cost caused by the remapping process is also considered, and can be calculated at the runtime to estimate the effect of remapping.

关键词： Network-on-chip Energy consumption mapping algorithm Online algorithm Migration

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An efficient task mapping algorithm with power-aware optimization for network on chip

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JOURNAL OF SYSTEMS ARCHITECTURE 2016年 70卷 48-58页

作者： Hu, Wei Shi, Qingsong Wang, Yonghao Zhang, Kai Liu, Jun Liu, Xiaoming Guo, Hong Wuhan Univ Sci & Technol Coll Comp Sci & Technol Wuhan 430065 Hubei Peoples R China Hubei Prov Key Lab Intelligent Informat Proc & Re Wuhan 430065 Hubei Peoples R China Zhejiang Univ Coll Comp Sci Hangzhou 310027 Zhejiang Peoples R China Birmingham City Univ Fac Comp Engn & Built Environm Ctr Digital Media Technol Birmingham W Midlands England

More and more cores are integrated onto a single chip to improve the performance and reduce the power consumption of CPU without the increased frequency. The cores are connected by lines and organized as a network, which is called network on chip (NOC) as the promising paradigm of the processor design. However, it is still a challenge to enhance performance with lower power consumption. The core issue is how to map the tasks to the different cores to take full advantages of the on-chip network. In this paper, we proposed a novel mapping algorithm with power-aware optimization for NOC. The traffic of the tasks will be analyzed. The tasks of the same application with high communication with the others will be mapped to the on-chip network as neighborhoods. And then the tasks of different applications are mapped to the cores step by step. The mapping of the tasks and the cores is computed at run-time dynamically and implement online. The experimental results showed that this proposed algorithm can reduce the power consumption in communication and the performance enhanced. (C) 2016 Elsevier B.V. All rights reserved.

关键词： Power consumption mapping algorithm Communication Network on chip

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Surface image generation using local slope-based mapping algorithm

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MICROWAVE AND OPTICAL TECHNOLOGY LETTERS 2000年第2期26卷 127-132页

作者： Pal, S Kak, SK Banaras Hindu Univ Inst Technol Dept Elect Engn Fiber Opt & Opt Commun Lab Varanasi 221005 Uttar Pradesh India

This paper introduces a novel technique to provide the microtopographical details of a machined surface using a fiber-optic probe. Unlike the previous methods, the present approach involves pixel-to-pixel scanning for slope measurement, which in him generates the three-dimensional profile of the probed surface using the relevant mapping algorithm. Minute details of the surface roughness characteristics including slope and height at different positions, can be visualized from the reconstructed surface image. (C) 2000 John Wiley & Sons, Inc.

关键词： fiber-optic sensors image sensors optical profilometer signal processing precision surface metrology surface roughness mapping algorithm

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Brightness improvement of color LCD systems using white sub-pixel structure and fuzzy mapping algorithm

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2007年第3期53卷 1003-1010页

作者： Lai, Chih-Chang Tsai, Ching-Chih Natl Chung Hsing Univ Dept Elect Engn Taichung 40227 Taiwan Wintek Corp Taichung Taiwan

This paper presents three novel color filter structures and a fuzzy mapping algorithm for improving brightness of color LCD systems. On the basis of human vision discrimination, the three color,filter structures with white sub-pixels are presented to enhance brightness of conventional stripe, Delta and PenTile color filter architectures without loss of their original color saturation and resolution. A new fuzzy mapping algorithm using RGB Sub-pixel data around white sub-pixels is proposed to obtain better image quality Numerous simulation and experimental results are provided to show the efficacy of the proposed structures and mapping method. The proposed techniques can be expected to be pragmatic and effective in designing color LCD display systems for electronic consumer products, such as notebooks, personal digital assistants, mobile phones and etc.

关键词： brightness color filter fuzzy logics LCD mapping algorithm

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Scalable Virtual Network mapping algorithm for Internet-Scale Networks

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IEICE TRANSACTIONS ON COMMUNICATIONS 2012年第7期E95B卷 2222-2231页

作者： Yang, Qiang Wu, Chunming Zhang, Min Zhejiang Univ Coll Elect Engn Hangzhou 310003 Zhejiang Peoples R China Zhejiang Univ Coll Comp Sci & Engn Hangzhou 310003 Zhejiang Peoples R China Zhejiang Univ Coll Comp Sci Hangzhou 310003 Zhejiang Peoples R China Zhejiang Univ Coll Comp Sci & Technol Hangzhou 310003 Zhejiang Peoples R China

The proper allocation of network resources from a common physical substrate to a set of virtual networks (VNs) is one of the key technical challenges of network virtualization. While a variety of state-of-the-art algorithms have been proposed in an attempt to address this issue from different facets, the challenge still remains in the context of large-scale networks as the existing solutions mainly perform in a centralized manner which requires maintaining the overall and up-to-date information of the underlying substrate network. This implies the restricted scalability and computational efficiency when the network scale becomes large. This paper tackles the virtual network mapping problem and proposes a novel hierarchical algorithm in conjunction with a substrate network decomposition approach. By appropriately transforming the underlying substrate network into a collection of sub-networks, the hierarchical virtual network mapping algorithm can be carried out through a global virtual network mapping algorithm (GVNMA) and a local virtual network mapping algorithm (LVNMA) operated in the network central server and within individual sub-networks respectively with their cooperation and coordination as necessary. The proposed algorithm is assessed against the centralized approaches through a set of numerical simulation experiments for a range of network scenarios. The results show that the proposed hierarchical approach can be about 5-20 times faster for VN mapping tasks than conventional centralized approaches with acceptable communication overhead between GVNCA and LVNCA for all examined networks, whilst performs almost as well as the centralized solutions.

关键词： virtual networks mapping algorithm Internet-scale networks hierarchical algorithm

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Optimized mapping algorithm to extend lifetime of both NoC and cores in many-core system

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INTEGRATION-THE VLSI JOURNAL 2019年 67卷 82-94页

作者： Wang, Lihuan Jiang, Shuyan Chen, Shuyu Wang, Junshi Huang, Letian Univ Elect Sci & Technol China Chengdu Sichuan Peoples R China

Fast aging of components has become one of the major concerns in Systems-on-Chip with further scaling of the submicron technology, which is accelerated when the working conditions are improper, such as unbalanced components' utilization. Moreover, in the process of the applications of mapping algorithm, the imbalance of component utilization is more likely to occur. The reason is that the mapping algorithm in the Network-on-Chip (NoC) domain may frequently select some routers/links for mapping while others are underutilized. Consequently, the highly utilized components may age faster than others that results in disconnecting the related cores from the network. To solve this problem, we have proposed a lifetime-aware mapping algorithm named LBC + LBL, which has simultaneously taken the aging of core and link into account when applying the mapping. In this paper, the lifetime is modeled as a resource consumed over time and a lifetime budget metric is accordingly defined. A suitable node, which has the maximum lifetime budget, is selected for mapping. Experimental results show that the proposed lifetime-aware mapping algorithm (LBC + LBL) could improve the minimal mean time to failure (MTTF) of NoC about 15.1%, compared with the mapping algorithm only considering the aging of cores.

关键词： Lifetime reliability Many-core system mapping algorithm Network-on-Chip

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Crinkle: A heuristic mapping algorithm for network on chip

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IEICE ELECTRONICS EXPRESS 2009年第24期6卷 1737-1744页

作者： Saeidi, Samira Khademzadeh, Ahmad Vardi, Fatemeh Islamic Azad Univ Sci & Res Branch CE Dept Tehran Iran Iran Telecom Res Ctr Tehran Iran

In this paper, a heuristic mapping algorithm which maps tasks, using priority lists and the crinkle moving pattern is proposed. To evaluate this algorithm, a set of real (i.e. Video Object Plan Decoder) and random applications have been used and the results have been compared. By reducing the number of hops between IP cores, the energy consumption and the completion time of the application (time which all tasks in the task graph execute wholly) have been optimized. Compared to other mapping algorithms, the algorithm execution time (due to its low complexity) is considerably lower.

关键词： network on chip task graph mapping algorithm energy consumption communication cost

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A hybrid mapping algorithm for reconfigurable nano-architectures

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JOURNAL OF ENGINEERING RESEARCH 2015年第1期3卷 79-93页

作者： Al-Mutairi, Hessa K. Ahmad, Imtiaz Kuwait Univ Dept Comp Engn Kuwait Kuwait

Nanotechnology is emerging as one of the most promising alternative technology to CMOS technology because of its higher density, high speed, lighter, and lower power consumption;however, defects are much higher in nanotechnology. Therefore, the need for defect-tolerance techniques becomes crucial in nanotechnology. This paper addresses an important intractable problem of finding a maximum size defect-free sub-crossbar in defective nano-scale crossbars for a higher yield. We propose a hybrid mapping algorithm by embedding known greedy heuristics with genetic algorithm (GA) to search a large solution space effectively. The proposed algorithm exploits the degrees of nodes, which play a crucial role in the selection mechanism in the greedy mapping heuristics to generate a better quality solution. In the proposed algorithm, GA provides the selection order by generating a new set of degrees that are used by the greedy mapping heuristic to find a new value for the defect-free sub-crossbar (k). The experimental results demonstrate the effectiveness of the proposed hybrid algorithm in finding a large size defect-free sub-crossbar compared to the existing state-of-the-art greedy heuristics.

关键词： Biclique problem defect tolerance genetic algorithm (GA) mapping algorithm nano-crossbar switches nanotechnology

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Energy- and Traffic-Balance-Aware mapping algorithm for Network-on-Chip

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2013年第3期E96D卷 719-722页

作者： Deng, Zhi Gu, Huaxi Yang, Yingtang You, Him Xidian Univ State Key Lab Integrated Serv Networks Xian 710071 Peoples R China Xidian Univ Sch Microelect Xian 710071 Peoples R China

In this paper, an energy- and traffic-balance-aware mapping algorithm from IP cores to nodes in a network is proposed for application-specific Network-on-Chip(NoC). The multi-objective optimization model is set up by considering the NoC architecture, and addressed by the proposed mapping algorithm that decomposes mapping optimization into a number of scalar subproblems simultaneously. In order to show performance of the proposed algorithm, the application specific benchmark is applied in the simulation. The experimental results demonstrate that the algorithm has advantages in energy consumption and traffic balance over other algorithms.

关键词： Network on Chip mapping algorithm multi-objective optimization energy consumption

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