Three Dimensional Network on Chip (3D NoC), which reduces the average number of hops traversed by a packet, can achieve better performance than the traditional 2D NoC. However, when routers deliver packets in 3D NoC, ...
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Three Dimensional Network on Chip (3D NoC), which reduces the average number of hops traversed by a packet, can achieve better performance than the traditional 2D NoC. However, when routers deliver packets in 3D NoC, more energy consumption is needed. High-energy consumption and small packaging density will cause excessive heat, which increases vulnerability of the system in performance and reliability. In this paper, we present a low-energy consumption mapping algorithm based on the symmetry of the architecture and construct a deadlock-free routing algorithm using mapping result information. Our proposed algorithms can reduce the total energy consumption of communication and achieve a good system performance under the bandwidth constraints. To evaluate the efficacy of the algorithms, we perform experiments on several benchmarks and compare the proposed algorithms with other existing algorithms. Experimental results show that, for complex benchmarks, our proposed algorithms get better results than others.
Network-on-Chips are now the popular communication medium to support inter-IP communications in complex on-chip systems with tens to hundreds IP cores. Higher scalability (compared to the traditional shared bus and po...
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Network-on-Chips are now the popular communication medium to support inter-IP communications in complex on-chip systems with tens to hundreds IP cores. Higher scalability (compared to the traditional shared bus and point-to-point interconnects), throughput, and reliability are among the most important advantages of NoCs. Moreover, NoCs can well match current CAD methodologies mainly relying on modular and reusable structures with regularity of structural pattern. However, since NoCs are resource-limited, determining how to distribute application load over limited on-chip resources (e.g. switches, buffers, virtual channels, and wires) in order to improve the metrics of interest and satisfy the application requirements becomes a challenging research issue known as topological mapping problem. This paper introduces a topological mapping strategy for direct networks. The Multi-Objective Genetic algorithm (MOGA) is used to obtain optimal Pareto-front of topological mapping solutions for an arbitrary network topology using a deadlock-free routing algorithm. Considered cost functions are the network latency and power consumption which are accurately estimated through two accurate analytical models. Before using the proposed analytical models in our MOGA method, we validate them through extensive simulation experiments, and compare their accuracy to some known models already proposed in the literature. We then quantitatively and qualitatively compare our analytical model based mapping method to two other methods: a genetic-based and a heuristic. Experimental evaluations using real workloads confirm that the proposed method is cost-efficient and can be used as a powerful tool for NoC design space exploration. Compared to the traditional mapping strategies, our mapping mechanism has the following advantages: (1) it greatly shortens the design period by using analytical models for fast and accurate predictions;(2) it can give a set of solutions, using MOGA, in terms of Pareto-
In Distributed Virtual Environment (DVE) systems, a distributed server infrastructure is often used to reduce the latency between servers and clients. Under this infrastructure, mapping clients to proper servers is on...
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ISBN:
(纸本)9780769538594
In Distributed Virtual Environment (DVE) systems, a distributed server infrastructure is often used to reduce the latency between servers and clients. Under this infrastructure, mapping clients to proper servers is one of the key issues for improving the interactivity and overall performance. Most traditional methods of mapping the clients to servers only consider the load balancing problem. However, there are two other important aspects that should be involved: the physical world integrity and the virtual world integrity. In this work, we propose a novel mapping algorithm which takes care of all three aspects at the same time. The algorithm converts the mapping problem into cutting stage and matching stage to get optimal result with polynomial complexity. The experimental results show that our algorithm improves the overall performance of DVE systems significantly.
The advancement in process technology has enabled integration of different types of processing cores into a single chip towards creating heterogeneous Multiprocessor Systems-on-Chip (MPSoCs). While providing high leve...
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ISBN:
(纸本)9780769550749
The advancement in process technology has enabled integration of different types of processing cores into a single chip towards creating heterogeneous Multiprocessor Systems-on-Chip (MPSoCs). While providing high level of computation power to support complex applications, these modern systems also introduce novel challenges for system designers, like managing a huge number of mappings (application tasks to processing cores allocations) that increases exponentially with the number of cores and their types. This paper presents a mapping approach that computes multiple energy-throughput trade-off points (mappings) at design-time and uses one of these points at run-time based on desired throughput and current resource availability while optimizing for the overall energy consumption. While significantly reducing the complexity of the design space exploration (DSE) to compute mappings at design-time, the proposed strategy still evaluates mappings for all the resource combinations of the platform, providing efficient mapping solutions for all the scenarios of system architecture at run-time. Moreover, the proposed approach performs energy-aware mapping at run-time while utilizing the DSE results. Experimental results show that proposed strategy achieves better energy-throughput trade-off points, covers all the resource combinations and reduces energy consumption up to 24.93% at design-time and additionally 17.8% at run-time when compared to state-of-the-art techniques.
This paper presents a vision-based localization and mapping algorithm for an autonomous mower. We divide the task for robotic mowing into two separate phases, a teaching phase and a mowing phase. During the teaching p...
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ISBN:
(纸本)9781467363563
This paper presents a vision-based localization and mapping algorithm for an autonomous mower. We divide the task for robotic mowing into two separate phases, a teaching phase and a mowing phase. During the teaching phase, the mower estimates the 3D positions of landmarks and defines a boundary in the lawn with an estimate of its own trajectory. During the mowing phase, the location of the mower is estimated using the landmark and boundary map acquired from the teaching phase. Of particular interest for our work is ensuring that the estimator for landmark mapping will not fail due to the nonlinearity of the system during the teaching phase. A nonlinear observer is designed with pseudo-measurements of each landmark's depth to prevent the map estimator from diverging. Simultaneously, the boundary is estimated with an EKF. Measurements taken from an omnidirectional camera, an IMU, and a ground speed sensor are used for the estimation. Numerical simulations and offline teaching phase experiments with our autonomous mower demonstrate the potential of our algorithm.
Attack graphs compute potential attack paths from a system configuration and known vulnerabilities of a system. Evidence graphs model intrusion evidence and dependencies among them. In this paper, we show how to map e...
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ISBN:
(纸本)9781467322850;9781467322867
Attack graphs compute potential attack paths from a system configuration and known vulnerabilities of a system. Evidence graphs model intrusion evidence and dependencies among them. In this paper, we show how to map evidence graphs to attack graphs. This mapping is useful for application of attack graphs and evidence graphs for forensic analysis. In addition to helping to refine attack graphs by using known sets of dependent attack evidence, important probabilistic information contained in evidence graphs can be used to compute or refine potential attack success probabilities obtained from repositories like CVSS. Conversely, attack graphs can be used to add missing evidence or remove irrelevant evidence trails to build a complete evidence graph. We illustrated the mapping by using a database attack as a case study.
Network on Chip (NoC) is proposed as a new intra-chip communication infrastructure. In current NoC design, one related problem is mapping IP cores onto NoC architectures. In this paper, we propose a performance-aware ...
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Network on Chip (NoC) is proposed as a new intra-chip communication infrastructure. In current NoC design, one related problem is mapping IP cores onto NoC architectures. In this paper, we propose a performance-aware hybrid algorithm (PHA) for mesh-based NoC to optimize performance indexes such as latency, energy consumption and maximal link bandwidth. The PHA is a hybrid algorithm, which integrates the advantages of Greedy algorithm, Genetic algorithm and Simulated Annealing algorithm. In the PHA, there are three features. First, it generates a fine initial population efficiently in a greedy swap way. Second, effective global parallel search is implemented by genetic operations such as crossover and mutation, which are implemented with adaptive probabilities according to the diversity of population. Third, probabilistic acceptance of a worse solution using simulated annealing method greatly improves the performance of local search. Compared with several previous mapping algorithms such as MOGA and TGA, simulation results show that our algorithm enhances the performance by 30.7%, 23.1% and 25.2% in energy consumption, latency and maximal link bandwidth respectively. Moreover, simulation results demonstrate that our PHA approach has the highest convergence speed among the three algorithms. These results show that our proposed mapping algorithm is more effective and efficient.
Canetti and Herzog have already proposed universally composable symbolic analysis(UCSA) to analyze mutual authentication and key exchange protocols. However,they do not analyze group key exchange protocol. Therefore,t...
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Canetti and Herzog have already proposed universally composable symbolic analysis(UCSA) to analyze mutual authentication and key exchange protocols. However,they do not analyze group key exchange protocol. Therefore,this paper explores an approach to analyze group key exchange protocols,which realize automation and guarantee the soundness of cryptography. Considered that there exist many kinds of group key exchange protocols and the participants’ number of each protocol is arbitrary. So this paper takes the case of Burmester-Desmedt(BD) protocol with three participants against passive adversary(3-BD-Passive) . In a nutshell,our works lay the root for analyzing group key exchange protocols automatically without sacrificing soundness of cryptography.
This paper presents three novel color filter structures and a fuzzy mapping algorithm for improving brightness of color LCD systems. On the basis of human vision discrimination, the three color,filter structures with ...
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This paper presents three novel color filter structures and a fuzzy mapping algorithm for improving brightness of color LCD systems. On the basis of human vision discrimination, the three color,filter structures with white sub-pixels are presented to enhance brightness of conventional stripe, Delta and PenTile color filter architectures without loss of their original color saturation and resolution. A new fuzzy mapping algorithm using RGB Sub-pixel data around white sub-pixels is proposed to obtain better image quality Numerous simulation and experimental results are provided to show the efficacy of the proposed structures and mapping method. The proposed techniques can be expected to be pragmatic and effective in designing color LCD display systems for electronic consumer products, such as notebooks, personal digital assistants, mobile phones and etc.
Network-on-Chip (NoC) architecture is drawing intensive attention since it promises to maintain high performance in handling complex communication issues as the number of on-chip components increases. An effective...
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Network-on-Chip (NoC) architecture is drawing intensive attention since it promises to maintain high performance in handling complex communication issues as the number of on-chip components increases. An effective method of mapping multitask applications on multicores is necessary to effectively use the NoC potential. In this paper, we propose an approach of quadratic programming (QP) formulation at the first time for the mapping problem, and it can overcome the unacceptable complexity of Integer Linear Programming (ILP) in dealing with problems with large size due to the decrease in the number of variables. Experimental results show that, QP method is at least 10 times faster than ILP method for 20 given benchmarks.
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