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Suitability of Different mapping algorithms for Genome-Wide Polymorphism Scans with Pool-Seq Data

G3-GENES GENOMES GENETICS 2016年第11期6卷 3507-3515页

作者： Kofler, Robert Langmueller, Anna Maria Nouhaud, Pierre Otte, Kathrin Anna Schloetterer, Christian Vetmeduni Vienna Inst Populat Genet Vet Pl 1 A-1210 Vienna Austria Vienna Grad Sch Populat Genet A-1210 Vienna Austria

The cost-effectiveness of sequencing pools of individuals (Pool-Seq) provides the basis for the popularity and widespread use of this method for many research questions, ranging from unraveling the genetic basis of complex traits, to the clonal evolution of cancer cells. Because the accuracy of Pool-Seq could be affected by many potential sources of error, several studies have determined, for example, the influence of sequencing technology, the library preparation protocol, and mapping parameters. Nevertheless, the impact of the mapping tools has not yet been evaluated. Using simulated and real Pool-Seq data, we demonstrate a substantial impact of the mapping tools, leading to characteristic false positives in genome-wide scans. The problem of false positives was particularly pronounced when data with different read lengths and insert sizes were compared. Out of 14 evaluated algorithms novoalign, bwa mem and clc4 are most suitable for mapping Pool-Seq data. Nevertheless, no single algorithm is sufficient for avoiding all false positives. We show that the intersection of the results of two mapping algorithms provides a simple, yet effective, strategy to eliminate false positives. We propose that the implementation of a consistent Pool-Seq bioinformatics pipeline, building on the recommendations of this study, can substantially increase the reliability of Pool-Seq results, in particular when libraries generated with different protocols are being compared.

关键词： Pool-Seq bioinformatics Next Generation Sequencing mapping algorithm Drosophila

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Application of validated mapping algorithms between generic PedsQL scores and utility values to individuals with sickle cell disease

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QUALITY OF LIFE RESEARCH 2022年第9期31卷 2729-2738页

作者： Jiao, Boshen Hankins, Jane S. Devine, Beth Barton, Martha Bender, M. Basu, Anirban Univ Washington Comparat Hlth Outcomes Policy & Econ CHOICE Inst 1959 NE Pacific StH-375QBox 357630 Seattle WA 98195 USA St Jude Childrens Res Hosp Dept Hematol 332 N Lauderdale St Memphis TN 38105 USA Univ Washington Dept Hlth Serv 1959 NE Pacific StH-375QBox 357630 Seattle WA 98195 USA Univ Washington Dept Pediat Seattle WA 98195 USA Fred Hutchinson Canc Res Ctr Clin Res Div 1124 Columbia St Seattle WA 98104 USA

Purpose There is a paucity of empirically estimated health state utility (HSU) values to estimate health-related quality of life among individuals with sickle cell disease (SCD). This study aims to map the Pediatric Quality of Life Inventory generic core scales (PedsQL GCS) to HSUs for children and adolescents with SCD in the United States, using published algorithms, and to assess the construct validity of these HSUs against SCD-specific PedsQL scores. Methods We used the published mapping algorithms identified in four published articles, in which the PedsQL GCS was mapped to either the EuroQol-5 Dimension 3-Level, Youth Version or the Child Health Utility 9-Dimension to obtain HSUs. We employed the algorithms to calculate HSUs for a sample of children and adolescents from the Sickle Cell Clinical Research and Intervention Program. To assess the construct validity of the mapped HSUs in SCD patients, we computed Spearman's correlation coefficient comparing the HSUs with the PedsQL SCD total score and separately with each PedsQL SCD dimension-specific score. Results The mean mapped HSU across published algorithms was 0.792 (95% CI: 0.782-0.801). It was significantly higher among children aged 5-12 years than children aged 13-17 years. The Spearman's correlation coefficient for HSUs versus PedsQL SCD total scores was 0.64 (95% CI: 0.57-0.71). Correlations ranged from 0.40 (95% CI: 0.32-0.48) to 0.60 (95% CI: 0.54-0.66) for HSUs versus PedsQL SCD dimension-specific scores. Conclusions The existing mapping algorithms show acceptable construct validity in children and adolescents with SCD. Additional algorithms are needed for adults and for specific SCD comorbidities.

关键词： Health state utility mapping algorithm PedsQL Sickle cell disease

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Bat algorithm Based Low Power mapping Methods for 3D Network-on-Chips 35th

Bat Algorithm Based Low Power Mapping Methods for 3D Network...

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35th National Conference of Theoretical Computer Science (NCTCS)

作者： Li, Jiazheng Song, Guozhi Ma, Yue Wang, Cheng Zhu, Baohui Chai, Yan Rong, Jieqi Tianjin Polytech Univ Sch Comp Sci & Software Engn Tianjin 300387 Peoples R China Univ Illinois Sch Informat Sci Champaign IL 61820 USA Yunnan Univ Sch Informat Sci Kunming 650500 Yunnan Peoples R China

ISBN: (纸本)9789811068935;9789811068928

mapping a task graph as a distribution of Intellectual Property (IP) cores onto a Network-on-Chip (NoC) is a NP-hard problem that significantly affects the performance metrics of the whole system including power, delay, load balance and heat. Intelligence optimization algorithms are widely used to solve mapping problems. Bat algorithm (BA), a novel metaheuristic algorithm mimicking hunting behaviors of bats, which has never been applied in NoCs, is used in low power mapping methods for 3D NoCs in this paper for the first time. The BA based mapping algorithm shows better performance than other mainstream mapping algorithms in terms of the optimization efficiency and power consumption. However, the concept of the basic BA has obvious disadvantages. To improve the basic BA, we propose a Group-Searching Bat algorithm (GSBA) that can better utilize individual bats. This improved mapping algorithm performs much better than the traditional BA, especially when the scale of the application graph is large.

关键词： Network-on-Chip mapping algorithm Low power Bat algorithm Parallel computing

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An Intelligent algorithm for mapping of Applications on Parallel Reconfigurable Systems 6

An Intelligent Algorithm for Mapping of Applications on Para...

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6th International Conference on Signal Processing and Intelligent Systems (ICSPIS)

作者： Rad, Masoud Yazdani Shahbandegan, Shakiba Iran Univ Sci & Technol Sch Elect Engn Tehran Iran

ISBN: (纸本)9781728186290

An increasing demand for computational power in daily used applications has led to implementation of different computing platforms. Among them, reconfigurable platforms which are based on FPGAs, have been widely used in recent years. While they are flexible, the communication cost between different computational tasks implemented in different locations of FPGA is one of the main challenges when it comes to improving the performance. In this paper, mapping of application tasks into processing platforms is studied. We presented a new method based on neural networks. Firstly, using Node2vec embedding algorithm, dimensions reduction, and rotation and scale, an initial mapping of task interaction graph nodes into processing structure FPGAs was obtained. Secondly, the dilation and maximum capacity utilization optimization were done using the stochastic gradient descent (SGD) method and loss functions. After performing experiments and comparing the proposed method with a similar method, results showed that the proposed method was superior in performance in terms of dilation (11.28%) and showed a poorer performance in terms of maximum capacity utilization (4.30%).

关键词： Intelligent algorithm reconfigurable computing task interaction graph stochastic gradient descent mapping algorithm

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Differential Spatial Modulation mapping algorithms

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ZTE Communications 2024年第3期22卷 116-122页

作者： WANG Chanfei CHAI Jianxin XU Yamei College of Computer and Communication Lanzhou University of Tech-nologyLanzhou 730050China

Differential spatial modulation(DSM)is a multiple-input multiple-output(MIMO)transmission *** has attracted extensive research interest due to its ability to transmit additional data without increasing any radio frequency *** this paper,DSM is investigated using two mapping algorithms:Look-Up Table Order(LUTO)and Permutation Method(PM).Then,the bit error rate(BER)performance and complexity of the two mapping algorithms in various antennas and modulation methods are verified by simulation *** results show that PM has a lower BER than the LUTO mapping algorithm,and the latter has lower complexity than the former.

关键词： spatial modulation(SM) multiple-input multiple-output(MIMO) Look-Up Table Order(LUTO) Permutation Method(PM) mapping algorithm

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Efficient mapping algorithms for survivable GMPLS networks

Efficient mapping algorithms for survivable GMPLS networks

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4th International Conference on Optical Networking and Communications

作者： Laborczi, P Arsenal Res A-1030 Vienna Austria

ISBN: (纸本)0819451800

With the advent of intelligent IP over optical networks, like GMPLS, connections can be protected against failures effectively;however, to capitalize the advantages, novel sophisticated methods are needed. This paper addresses the task of finding efficient mapping in a survivable multilayer network in order to ensure high availability for connections. Known methods (like running a shortest path algorithm) do not consider finding physically disjoint paths in the upper layer and thus cause failure propagation. Besides formulating the problem, we propose a randomized heuristic method to solve it. The quality of the solution is evaluated (1) by the number of node-pairs for which a physically-disjoint path-pair can be found in the upper layer, or (2) by the number of spans used by both working and protection paths (i.e., failure propagation effect). It is shown with numerous simulations that our proposed method finds solution for significantly more node pairs (86% instead of 45% in the 35-node network) than traditional methods. Furthermore, it yields connection availabilities near to the optimum.

关键词： mapping algorithm multilayer networks disjoint routing

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3D NoC Low-Power mapping Optimization Based on Improved Genetic algorithm

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MICROMACHINES 2021年第10期12卷 1217-1217页

作者： Gan, Yu Guo, Hong Zhou, Ziheng Wuhan Univ Sci & Technol Coll Comp Sci & Technol Wuhan 430065 Hubei Peoples R China

Power optimization is an important part of network-on-chip(NoC) design. This paper proposes an improved algorithm based on genetic algorithm on how to properly map IP (Intellectual Property) cores to 3D NoC. First, in view of the randomness of the traditional genetic algorithm in individual selection, an improved greedy algorithm is used in the initial population generation stage to make the generated individuals reach the optimal. Secondly, in view of the weak local optimization ability of the traditional genetic algorithm and prone to premature problems, the simulated annealing algorithm is added in the crossover operation stage to make the offspring reach the global optimum. The experimental results show that compared with the traditional genetic algorithm, the algorithm has better convergence and low power consumption performance, which can quickly search for a better solution, in the case of a large number of cores (124 IP cores), the average power consumption can be reduced by 42.2%.

关键词： 3D NoC low power consumption mapping algorithm improved genetic algorithm population optimization global optimization

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An algorithm for mapping loops onto coarse-grained reconfigurable architectures 03

An algorithm for mapping loops onto coarse-grained reconfigu...

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Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems

作者： Jong-eun Lee Kiyoung Choi Nikil D. Dutt EECS Seoul National University Seoul Korea University of California Irvine CA

ISBN: (纸本)9781581136470

With the increasing demand for flexible yet highly efficient architecture platforms for media applications, there is a growing interest in the Coarse-grained Reconfigurable Architectures (CRAs). While many CRAs have demonstrated impressive performance improvement, the lack of compilation technology for such architectures causes a bottleneck in the current design process. In this paper, we present a novel mapping algorithm designed to support Reconfigurable ALU Array (RAA) architectures, that represent a significant class of CRAs. More specifically we present a core mapping algorithm that addresses the problem of placing and routing the operations of a loop body onto the ALU array, to be executed in a loop pipelined fashion. Experimental results using our mapping algorithm on a typical RAA show that our algorithm not only has very fast compilation time but can also generate quality mappings exhibiting high memory bandwidth utilization and low global interconnection requirements. Comparison with manual mapping also indicates that our algorithm can generate near-optimal mappings for several loops.

关键词： ALU array memory bandwidth utilization mapping algorithm coarse-grained reconfigurable architecture

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Reliability-aware mapping for various No C topologies and routing algorithms under performance constraints

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Science China(Information Sciences) 2015年第8期58卷 168-181页

作者： WU Chen DENG ChenChen LIU LeiBo YIN ShouYi HAN Jie WEI ShaoJun National Lab for Information Science and Technology Tsinghua University ECE Department University of Alberta

The flexibility of manycore systems to extensive applications is achieved by reconfiguring the interconnections between processing elements(PEs) and the function of PEs. The efficiency of the system is crucially determined by the mapping technique of applications. In this paper, a highly flexible reliability-aware application mapping approach is proposed for manycore network-on-chip(No C) systems. A reliability cost model(RCM) is first presented to measure the reliability cost for a mapping pattern. This model uses the binary number 0/1 to model the reliability cost of each communication path. The overall reliability cost of a mapping pattern is evaluated by taking the cost of each path as a discrete random variable. Based on RCM,a mapping method called reliability cost ratio based branch and bound(RCRBB) is used. With this method,the best mapping among all the possible patterns is found efficiently by discarding those nonoptimal candidate mappings at early stages. The proposed application mapping approach with reliability awareness is applicable to various No C topologies and routing algorithms, while other state-of-the-art approaches on the same topic are only limited to a specific topology and routing algorithm. Even for the same No C architecture, the proposed approach shows significant superiority in many aspects. Experiments show that RCRBB achieves up to 9.07%reliability enhancement on average. Also, it outperforms other approaches in throughput and latency with a relatively low run time.

关键词： reliability-aware network-on-chip(No C) mapping algorithm performance flexibility

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Testing aware dynamic mapping for path-centric network-on-chip test

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INTEGRATION-THE VLSI JOURNAL 2019年第Jul.期67卷 134-143页

作者： Jiang, Shuyan Wu, Qiong Chen, Shuyu Zhan, Junkai Wang, Junshi Ebrahimi, Masoumeh Huang, Letian Univ Elect Sci & Technol China Chengdu Sichuan Peoples R China Royal Inst Technol KTH Stockholm Sweden

With the aggressive scaling of submicron technology, intermittent faults are becoming one of the limiting factors in achieving high reliability in Network-on-Chip (NoC). Increasing test frequency is necessary to detect intermittent faults, which in turn interrupts the execution of applications. On the other hand, the primary goal of traditional mapping algorithms is to allocate applications to the NoC platform, ignoring the test requirement. In this paper, we propose a novel testing-aware mapping algorithm (TAMA) for NoC, targeting intermittent faults on the paths between crossbars. In this approach, the idle paths are identified, and the components between two crossbars are tested when the application is mapped to the platform. The components can be tested if there is enough time from the time when the application leaves the platform to the time when a new application enters it. The mapping algorithm is tuned to give a higher priority to the tested paths in the next application mapping, which leaves enough time to test the links and the belonging components that have not been tested in the expected time. Experiment results show that the proposed testing-aware mapping algorithm leads to a significant improvement over FF(Fiexitrst Free), NN(Nearest Neighbor), CoNA(Contiguous Neighborhood Allocation), and WeNA(Weighted-based Neighborhood Allocation).

关键词： Network-on-Chip mapping algorithm Intermittent fault On-line testing

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