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PATTERN RECOGNITION 1980年第3期12卷 127-136页

作者： GELSEMA, ES EDEN, G Department of Medical Informatics Free University Van der Boechorstraat 7 Amsterdam The Netherlands[∗]Now at the Biomedical Engineering Center Massachusetts Institute of Technology Cambridge Massachusetts 02139.

A number of mapping operations in pattern recognition is reviewed. Two families of new mapping algorithms are defined. The performance of all algorithms is illustrated using a collection of 100 feature vectors obtained from images of two classes of white blood cells. It is emphasized that the interactive pattern recognition system ISPAHAN is well suited to find optimal decision functions based on such mappings.

关键词： ISPAHAN mapping algorithms Dimensionality reduction Pattern classification Interactive pattern recognition

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mapping algorithms for NoC-based Heterogeneous MPSoC Platforms

Mapping Algorithms for NoC-based Heterogeneous MPSoC Platfor...

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12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

作者： Singh, Amit Kumar Wu Jigang Prakash, Alok Srikanthan, Thambipillai Nanyang Technol Univ Ctr High Performance Embedded Syst Singapore Singapore

ISBN: (纸本)9780769537825

mapping of applications onto Multiprocessor System-on-Chip (MPSoC) can be realized either at design-time or run-time. At any time the number of tasks executing in MPSoC platform can exceed the available resources, requiring efficient run-time mapping techniques to meet the real-time constraints of the applications. This paper presents two run-time mapping heuristics for mapping the tasks of an application in close proximity so as to minimize the communication overhead. In particular, the communication overhead between two adjacent hardware tasks is eliminated by mapping them onto the same reconfigurable processing node. We show that the proposed approach is capable of alleviating Network-on-Chip (NoC) congestion bottlenecks to optimize the overall performance. Based on our investigations to map the tasks of applications' at run-time onto an 8x8 NoC-based Heterogeneous MPSoC, our mapping heuristics are capable of reducing total execution time and average channel load of applications when compared to state-of-the-art run-time mapping heuristics.

关键词： Multiprocessor System-on-Chip (MPSoC) Design Network-on-Chip (NoC) Run-time mapping mapping algorithms

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A comparison of mapping algorithms for hierarchical adaptive FEM in finite elasto-plasticity

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COMPUTATIONAL MECHANICS 2007年第4期39卷 521-536页

作者： Bucher, A. Meyer, A. Goerke, U. -J. Kreissig, R. Tech Univ Chemnitz Dept Math D-09111 Chemnitz Germany

The aim of this contribution is a comparison of different mapping techniques usually applied in the field of hierarchical adaptive FE-codes. The calculation of mechanical field variables for the modified mesh is an important but sensitive aspect of adaptation approaches of the spatial discretization. Regarding non-linear boundary value problems procedures of mesh refinement and coarsening imply the determination of strains, stresses and internal variables at the nodes and the Gauss points of new elements based on the transfer of the required data from the former mesh. The kind of mapping of the field variables affects the convergence behaviour as well as the costs of an adaptive FEM-calculation in a non-negligible manner. In order to improve the stability as well as the efficiency of the adaptive process a comparison of different mapping algorithms is presented and evaluated. Within this context, the mapping methods taken into account are an element-oriented extrapolation procedure using special shape functions, a patch-oriented transfer approach and, the allocation of nodal history-dependent state (field) variable data using a supplementary integration of the material law at the nodes of the elements.

关键词： FEM adaptivity mapping algorithms finite deformations elasto-plasticity

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Underestimation of Uncertainties in Health Utilities Derived from mapping algorithms Involving Health-Related Quality-of-Life Measures: Statistical Explanations and Potential Remedies

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MEDICAL DECISION MAKING 2014年第7期34卷 863-872页

作者： Chan, Kelvin K. W. Willan, Andrew R. Gupta, Michael Pullenayegum, Eleanor Univ Toronto Sunnybrook Hlth Sci Ctr Div Med Oncol Dept MedFac Med Toronto ON Canada Univ Toronto Div Biostat Dalla Lana Sch Publ Hlth Toronto ON Canada McMaster Univ Dept Surg Hamilton ON L8S 4L8 Canada McMaster Univ Dept Clin Epidemiol & Biostat Hamilton ON Canada

Objectives. mapping algorithms are being developed in increasing numbers to derive health utilities (HUs) from health-related quality-of-life (HRQOL) data. However, the variances of the mapping-derived HUs are observed to be smaller than those of the actual HUs. Methods. Two reasons are proposed: 1) the presence of important unmeasured predictors leading to a high degree of unexplained variance and 2) ignoring that the regression coefficients are random variables themselves. We derive 3 variance estimators of HUs to account for these causes: 1) R-2-adjusted estimator, 2) parametric estimator, and 3) nonparametric estimator. We tested these estimators using a simulated dataset and a real dataset involving the EQ-5D-3L and University of Washington Quality of Life questionnaire for patients with head and neck cancers. Results. The R-2-adjusted estimator can be used in ordinary least squares (OLS)-based mapping algorithms and requires only the R-2 from the derivation study. The parametric estimator can be used in OLS-based mapping algorithms and requires the mean square error (MSE) and design matrix from the derivation study. The nonparametric estimator can be used in any mapping algorithm and requires leave-one-out cross-validation MSE from the derivation study. In the simulated dataset, all 3 estimators are within 1% of the variance of the actual HUs. In the real dataset, the unadjusted variance was 45% less than the actual variance, while all 3 estimators are within 10% of the actual variance. Conclusions. When conducting cost-utility analyses (CUA) based on mapping algorithms, the variances of derived HUs should be properly adjusted using one of the proposed methods so that the results of the CUAs will correctly characterize uncertainty.

关键词： health utilities variance estimation mapping algorithms

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Comparison of mapping algorithms used in high-throughput sequencing: application to Ion Torrent data

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BMC GENOMICS 2014年第1期15卷 1-16页

作者： Caboche, Segolene Audebert, Christophe Lemoine, Yves Hot, David Inst Pasteur CNRS FRE Mol & Cellular Med 3642 F-59019 Lille France Univ Lille Nord France F-59019 Lille France Genes Diffus F-59501 Douai France Univ Lille Nord France Inst Pasteur Lille CNRS UMR8204InsermU1019Ctr Infect & Immun Lille Lille France Inst Pasteur PEGASE Biosci F-59019 Lille France

Background: The rapid evolution in high-throughput sequencing (HTS) technologies has opened up new perspectives in several research fields and led to the production of large volumes of sequence data. A fundamental step in HTS data analysis is the mapping of reads onto reference sequences. Choosing a suitable mapper for a given technology and a given application is a subtle task because of the difficulty of evaluating mapping algorithms. Results: In this paper, we present a benchmark procedure to compare mapping algorithms used in HTS using both real and simulated datasets and considering four evaluation criteria: computational resource and time requirements, robustness of mapping, ability to report positions for reads in repetitive regions, and ability to retrieve true genetic variation positions. To measure robustness, we introduced a new definition for a correctly mapped read taking into account not only the expected start position of the read but also the end position and the number of indels and substitutions. We developed CuReSim, a new read simulator, that is able to generate customized benchmark data for any kind of HTS technology by adjusting parameters to the error types. CuReSim and CuReSimEval, a tool to evaluate the mapping quality of the CuReSim simulated reads, are freely available. We applied our benchmark procedure to evaluate 14 mappers in the context of whole genome sequencing of small genomes with Ion Torrent data for which such a comparison has not yet been established. Conclusions: A benchmark procedure to compare HTS data mappers is introduced with a new definition for the mapping correctness as well as tools to generate simulated reads and evaluate mapping quality. The application of this procedure to Ion Torrent data from the whole genome sequencing of small genomes has allowed us to validate our benchmark procedure and demonstrate that it is helpful for selecting a mapper based on the intended application, questions to be addressed, and the

关键词： High-throughput sequencing mapping algorithms Mapper comparison Read simulator

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BindMe: A thread binding library with advanced mapping algorithms

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2018年第21期30卷

作者： Soomro, Pirah Noor Sasongko, Muhammad Aditya Unat, Didem Koc Univ Comp Sci & Engn Istanbul Turkey

Binding parallel tasks to cores according to a placement policy is one of the key aspects to achieve good performance in multicore machines because it can reduce on-chip communication among parallel threads. Binding also prevents operating system from migrating threads, which improves data locality. However, there is no single mapping policy that works best among all different kinds of applications and platforms because each machine has a different topology and each application exhibits different communication pattern. Determining the best policy for a given application and machine requires extra programming effort. To relieve the programmer from that burden, we introduce BindMe, a thread binding library that assists programmer to bind threads to underlying hardware. BindMe incorporates state-of-the-art mapping algorithms, which use communication pattern in an application to formulate an efficient task placement policy. We also introduce ChoiceMap, a communication aware mapping algorithm that respects mutual priorities of parallel tasks and performs a fair mapping by reducing communication volume among cores. We have tested BindMe and ChoiceMap with various applications from NAS parallel benchmark and Rodinia bechmark. Our results show that choosing a mapping policy that best suits the application behavior can increase its performance and no single policy gives the best performance across different applications.

关键词： communication matrix machine topology mapping algorithms multicore task binding

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Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms

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JOURNAL OF SYSTEMS ARCHITECTURE 2010年第7期56卷 242-255页

作者： Singh, Amit Kumar Srikanthan, Thambipillai Kumar, Akash Wu Jigang Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore Natl Univ Singapore Dept Elect & Comp Engn Singapore 117548 Singapore Eindhoven Univ Technol Dept Elect Engn NL-5600 MB Eindhoven Netherlands

Efficient run-time mapping of tasks onto Multiprocessor System-on-Chip (MPSoC) is very challenging especially when new tasks of other applications are also required to be supported at run-time. In this paper, we present a number of communication-aware run-time mapping heuristics for the efficient mapping of multiple applications onto an MPSoC platform in which more than one task can be supported by each processing element (PE). The proposed mapping heuristics examine the available resources prior to recommending the adjacent communicating tasks on to the same PE. In addition, the proposed heuristics give priority to the tasks of an application in close proximity so as to further minimize the communication overhead. Our investigations show that the proposed heuristics are capable of alleviating Network-on-Chip (NoC) congestion bottlenecks when compared to existing alternatives. We map tasks of applications onto an 8 x 8 NoC-based MPSoC to show that our mapping heuristics consistently leads to reduction in the total execution time, energy consumption, average channel load and latency. In particular, we show that energy savings can be up to 44% and average channel load is improved by 10% for some cases. (C) 2010 Elsevier B.V. All rights reserved.

关键词： Hardware-software co-design Heterogeneous architectures MPSoC design Network-on-Chip (NoC) mapping algorithms

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A new task graph model for mapping message passing applications

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2007年第12期18卷 1740-1753页

作者： Roig, Concepcio Ripoll, Ana Guirado, Fernando Univ Lleida Dept Comp Sci Escola Politecn Super Lleida 25001 Spain Univ Autonoma Barcelona Dept Comp Architecture Escola Tecn Super Engn Bellaterra 08193 Spain

The exploitation of parallelism in a message passing platform implies a previous modeling phase of the parallel application as a task graph, which properly reflects its temporal behavior. In this paper, we analyze the classical task graph models of the literature and their drawbacks when modeling message passing programs with an arbitrary task structure. We define a new task graph model called Temporal Task Interaction Graph ( TTIG) that integrates the classical models used in the literature. The TTIG allows us to explicitly capture the ability of concurrency of adjacent tasks for applications where adjacent tasks can communicate at any point inside them. A mapping strategy is developed from this model, which minimizes the expected execution time by properly exploiting task parallelism. The effectiveness of this approach has been proved in different experimentation scopes for a wide range of message passing applications.

关键词： task graphs modeling message passing programs program behavior task concurrency static mapping mapping algorithms

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mapping of tubular woven composite preforms on to doubly-curved surfaces

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COMPUTER-AIDED DESIGN 2001年第14期33卷 1035-1048页

作者： Sharma, SB Potluri, P Atkinson, J Porat, I UMIST Dept Text & Mech Engn Manchester M60 1QD Lancs England

This paper deals with the drape behaviour of tubular woven fabric hoses over doubly curved mould surfaces. The primary aim of this analysis is to predict the alignment of the constituent fibres over the mould surface, which in composites-based applications directly influences the quality of the final product in terms of its structural homogeneity and mechanical properties. Previous work in the area has resulted in algorithms to map the fibres of a flat woven fabric over open surfaces using the shear deformation theory of a woven lamina. The present paper first applies these algorithms to map a flat fabric on to a doubly curved tubular surface and determines the outline of an equivalent tubular fabric preform needed to cover the surface. It is noted that using such a mapping, even to produce a simple u-bend tube requires the tubular preform to have varying cross-section, which is difficult to manufacture. Subsequently, specific algorithms are developed to map a straight tubular hose over a bent and twisted tubular section. Using basic principles of mechanics, models have been derived to map the mesh of fibres over geodesic paths on the curved surface. It is noted that shear deformation plays little or no role but fabric extension and buckling play major roles. The resulting mapping algorithm has been applied to several shapes of varying complexity and experimental validations have been performed. (C) 2001 Elsevier Science Ltd. All rights reserved.

关键词： composites fabric drape mapping algorithms woven preforms

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mapping techniques in multicore processors: current and future trends

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JOURNAL OF SUPERCOMPUTING 2021年第8期77卷 9308-9363页

作者： Gupta, Manjari Bhargava, Lava Indu, S. Malaviya Natl Inst Technol Jaipur Rajasthan India Delhi Technol Univ Delhi India

Multicore systems are in demand due to their high performance thus making application mapping an important research area in this field. Breaking an application into multiple parallel tasks efficiently and task-core assignment decisions can drastically influence system performance. This has created an urgency to find potent mapping techniques which can handle the complexity of these systems. Task assignment methods are governed by the application model, user-requirements, and architecture model. This paper provides an overview and classification of mapping algorithms that would facilitate graphical interpretation of the known techniques. It details the mapping methodologies along with performance, energy consumption, communication cost, reliability, or thermal management on different target architectures. Upcoming trends and open research areas have also been discussed.

关键词： mapping algorithms Multicore processors Run-time mapping Design-time mapping Survey

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