This research is devoted to the study and analysis of modern methods of building routes. The article describes the data provided by the Open street map, google maps API and ways of working with them, as well as variou...
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ISBN:
(纸本)9781665404761
This research is devoted to the study and analysis of modern methods of building routes. The article describes the data provided by the Open street map, google maps API and ways of working with them, as well as various routing algorithms used in Graphhopper, ***, and other routing services. In the course of the study, based on the material studied about working with maps, graphs, and routing services, a web application was created. It is aimed at solving the problem of optimizing the route for the needs of the user.
The FPGA logic block mapping algorithm described in this paper is based on numerical sequence matching. Numerical sequences are generated under certain rules to represent each functional circuit of the FPGA's logi...
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ISBN:
(纸本)9781424457977
The FPGA logic block mapping algorithm described in this paper is based on numerical sequence matching. Numerical sequences are generated under certain rules to represent each functional circuit of the FPGA's logic block and the user's input circuit. The mapping procedure is conducted by matching the sequence of the input circuits and the logic block. This algorithm can be applied for different types of LUT logic blocks. The complexity of this algorithm is O (n2), where n is the sum of the net nodes of the input circuit, which requires far less running time than the similar matching algorithms. A "compact degree" is also introduced in this paper, which shows a fine result of area saving.
This paper shows how to parallelize tree-structured computations for d-dimensional (d > 1) mesh-connected arrays of processors. A tree-structured computation T consists of n computational tasks whose dependencies f...
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Deep Neural Networks (DNN) have shown significant advantages in many domains such as pattern recognition, prediction, and control optimization. The edge computing demand in the Internet-of-Things era has motivated man...
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ISBN:
(纸本)9781450367004
Deep Neural Networks (DNN) have shown significant advantages in many domains such as pattern recognition, prediction, and control optimization. The edge computing demand in the Internet-of-Things era has motivated many kinds of computing platforms to accelerate the DNN operations. The most common platforms are CPU, GPU, ASIC, and FPGA. However, these platforms suffer from low performance (i.e., CPU and GPU), large power consumption (i.e., CPU, GPU, ASIC, and FPGA), or low computational flexibility at runtime (i.e., FPGA and ASIC). In this paper, we suggest the NoC-based DNN platform as a new accelerator design paradigm. The NoC-based designs can reduce the off-chip memory accesses through a flexible interconnect that facilitates data exchange between processing elements on the chip. We first comprehensively investigate conventional platforms and methodologies used in DNN computing. Then we study and analyze different design parameters to implement the NoC-based DNN accelerator. The presented accelerator is based on mesh topology, neuron clustering, random mapping, and XY-routing. The experimental results on LeNet, MobileNet, and VGG-16 models show the benefits of the NoC-based DNN accelerator in reducing off-chip memory accesses and improving runtime computational flexibility.
Motivated by distributed control and sensor network applications in Electric Energy Systems, we consider the problem of estimation via a communication network. When data is sent via communication channels in a large, ...
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Motivated by distributed control and sensor network applications in Electric Energy Systems, we consider the problem of estimation via a communication network. When data is sent via communication channels in a large, wireless, multi-sensor network, the effect of communication constraints on estimation performance, such as communication delay and asynchronous irregular sampling, have to be considered. In this thesis we formulate a delay mitigation method based on a Kalman filter with time-stamping technology, which transmutes communication delay into increased estimation error, so that the closed-loop control system remains stable even in the presence of significant delay. The resulting signal to estimation error ratio (SEER), at any point in the estimation-control loop, is a monotone decreasing function of the average communication delay. When the sensor sampling patterns (SSP) are irregular and asynchronous, the SEER is a monotone decreasing function in each one of the average sampling intervals, with very minor dependence on higher order moments of this interval. The best performance is achieved when the individual SSPs are regular and aligned in such a way that the superposed set of sampling instants is as close to regular as possible. In particular, synchronized regular sampling (i.e., all sensors sampled regularly at the same time instants) is inferior to uniformly staggered regular sampling, in which the sampling instants of individual sensors are spaced evenly within a single sampling interval.
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