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19th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)

作者： Walter, Dominik Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg Hardware Software Codesign Erlangen Germany

ISBN: (纸本)9781450391276

The performance of many accelerator architectures depends on the communication with external memory. During execution, new I/O data is continuously fetched forth and back to memory. This data exchange is very often performance-critical and a careful orchestration thus vital. To satisfy the I/O demand for accelerators of loop nests, it was shown that the individual reads and writes can be merged into larger blocks, which are subsequently transferred by a single DMA transfer. Furthermore, the order in which such DMA transfers must be issued, was shown to be reducible to a real-time task scheduling problem to be solved at run time. Rather than just concepts, we investigate in this paper efficient algorithms, data structures and their implementation in hardware of such a programmable Loop I/O Controller architecture called LION that only needs to be synthesized once for each processor array size and I/O buffer configuration, thus supporting a large class of processor arrays. Based on a proposed heap-based priority queue, LION is able to issue every 6 cycles a new DMA request to a memory bus. Even on a simple FPGA prototype running at just 200 MHz, this allows for more than 33 million DMA requests to be issued per second. Since the execution time of a typical DMA request is in general at least one order of magnitude longer, we can conclude that this rate is sufficient to fully utilize a given memory interface. Finally, we present implementations on FPGA and also 22nm FDX ASIC showing that the overall overhead of a LION typically amounts to less than 5% of an overall processor array design.

关键词： massively parallel processor arrays TCPA I/O Scheduling Data Transfers Priority QueueZ

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Decentralized Dynamic Resource Management Support for massively parallel processor arrays

Decentralized Dynamic Resource Management Support for Massiv...

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22nd IEEE International Conference on Application-Specific Systems, Architectures and processors (ASAP)

作者： Lari, Vahid Narovlyanskyy, Andriy Hannig, Frank Teich, Juergen Univ Erlangen Nurnberg Dept Comp Sci Hardware Software Co Design Erlangen Germany

ISBN: (纸本)9781457712920

This paper presents a hardware-supported resource management methodology for massively parallel processor arrays. It enables processing elements to autonomously explore resource availability in their neighborhood. To support resource exploration, we introduce specialized controllers, which can be attached to each of the processing elements. We propose different types of architectures for the exploration controller: fast FSM-based designs as well as flexible programmable controllers. These controllers allow to implement different distributed resource exploration strategies in order to enable parallel programs the exploration and reservation of available resources according to different application requirements. Hardware cost evaluations show that the cost of the simplest implementation of our programmable controller is comparable to our FSM-based implementations, while offering the flexibility for implementing different exploration strategies. We show that the proposed distributed approach can achieve a significant speedup in comparison with centralized resource exploration methods.

关键词： arrays FSM-based designs Hardware Registers centralized resource exploration methods decentralized dynamic resource management support distributed resource exploration strategies hardware cost evaluations hardware-supported resource management methodology many-core architectures massively parallel processor arrays multicore architectures multiprocessing systems parallel programming parallel programs programmable controllers programmable controllers resource allocation

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Providing fault tolerance through invasive computing

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IT-INFORMATION TECHNOLOGY 2016年第6期58卷 309-328页

作者： Lari, Vahid Weichslgartner, Andreas Tanase, Alexandru Witterauf, Michael Khosravi, Faramarz Teich, Juergen Heisswolf, Jan Friederich, Stephanie Becker, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Hardware Software Codesign Cauerstr 11 D-91058 Erlangen Germany Robert Bosch GmbH Tuebingerstr 123 D-72762 Reutlingen Germany Karlsruhe Inst Technol Inst Informat Proc Technol ITIV Engesserstr 5 D-76131 Karlsruhe Germany

As a consequence of technology scaling, today's complex multi-processor systems have become more and more susceptible to errors. In order to satisfy reliability requirements, such systems require methods to detect and tolerate errors. This entails two major challenges: (a) providing a comprehensive approach that ensures fault-tolerant execution of parallel applications across different types of resources, and (b) optimizing resource usage in the face of dynamic fault probabilities or with varying fault tolerance needs of different applications. In this paper, we present a holistic and adaptive approach to provide fault tolerance on Multi-processor System-on-a Chip (MPSoC) on demand of an application or environmental needs based on invasive computing. We show how invasive computing may provide adaptive fault tolerance on a heterogeneous MPSoC including hardware accelerators and communication infrastructure such as a Network-on-Chip (NoC). In addition, we present (a) compile-time transformations to automatically adopt well-known redundancy schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) for fault-tolerant loop execution on a class of massively parallel arrays of processors called as Tightly Coupled processor arrays (TCPAs). Based on timing characteristics derived from our compilation flow, we further develop (b) a reliability analysis guiding the selection of a suitable degree of fault tolerance. Finally, we present (c) a methodology to detect and adaptively mitigate faults in invasive NoCs.

关键词： Heterogeneous MPSoC adaptive fault tolerance structural redundancy network-on-chip massively parallel processor arrays resource-aware parallel programming

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Efficient Baseband Modem Physical Implementation for Fixed Broadband Wireless Access Networks 5

Efficient Baseband Modem Physical Implementation for Fixed B...

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5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

作者： Bisdounis, Labros Technol Educ Inst TEI Western Greece Dept Elect Engn Patras Greece

ISBN: (纸本)9781467396806

This paper presents the physical implementation of the digital part of an OFDM-based baseband modem for point-to-multipoint fixed broadband wireless access (FBWA) solutions. It is compliant with the corresponding IEEE 802.16 standard and compatible to a fixed WiMAX profile. The adopted realization approach is based on an array of processing elements belonging to a case of computing systems characterized by having hundreds of embedded processing elements and memories (massively parallel processor arrays). The approach offers the performance, the computational density and the programmability needed for the implementation of modern wireless communication systems.

关键词： baseband modem broadband access networks wireless communication systems IEEE 802.16 WiMAX OFDM massively parallel processor arrays

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An FPGA-Based Reconfigurable Mesh Many-Core

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IEEE TRANSACTIONS ON COMPUTERS 2014年第12期63卷 2919-2932页

作者： Giefers, Heiner Platzner, Marco IBM Res Zurich CH-8803 Ruschlikon Switzerland Univ Paderborn Dept Comp Sci D-33098 Paderborn Germany

The reconfigurable mesh is a parallel model of computation, which exploits a massive amount of rather simple processing elements connected through a reconfigurable interconnection network. During the last decades, the model received strong interest and many researchers have devised algorithms for it. However, most of this work focuses on theoretical aspects. Due to some idealistic modeling assumptions only a few attempts have been made to implement the model and to study the practical use of reconfigurable meshes. In this paper, we leverage the reconfigurable mesh model to study potential architectures and programming models for future many-cores. We design a reconfigurable mesh in form of a scalable soft core array with a reconfigurable interconnect and implement it on FPGA technology in order to create a prototype platform. We present an overall hardware/software tool flow for generating and programming reconfigurable mesh prototypes. The new language ARMLang and a corresponding compiler facilitate the programming of the massively parallel processor arrays. To our knowledge, this work is the first practical study of word-level reconfigurable meshes. To analyze the performance of our implementation we study four algorithmic kernels from the application domains arithmetic, sorting, graph algorithms and imaging. For each kernel, we devise a reconfigurable mesh program in ARMLang, compile it to our soft core array and measure its runtime depending on the mesh size. Then, we compare the runtimes to two sequential implementations of the algorithms, which are executed on two single core systems. The results show that many-cores leveraging the reconfigurable mesh model can efficiently use a vast number of processing elements and that, for the chosen algorithms, they come close to optimally parallelized programs.

关键词： Reconfigurable mesh FPGA many-core reconfigurable architectures massively parallel processor arrays

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Compact Code Generation for Tightly-Coupled processor arrays

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2014年第1-2期77卷 5-29页

作者： Boppu, Srinivas Hannig, Frank Teich, Juergen Univ Erlangen Nurnberg Dept Comp Sci D-91058 Erlangen Germany

In this paper, we consider programmable tightly-coupled processor arrays consisting of interconnected small light-weight VLIW cores, which can exploit both loop-level parallelism and instruction-level parallelism. These arrays are well suited for compute-intensive nested loop applications often providing a higher power and area efficiency compared with commercial off-the-shelf processors. They are ideal candidates for accelerating the computation of nested loop programs in future heterogeneous systems, where energy efficiency is one of the most important design goals for overall system-on-chip design. In this context, we present a novel design methodology for the mapping of nested loop programs onto such processor arrays. Key features of our approach are: (1) Design entry in form of a functional programming language and loop parallelization in the polyhedron model, (2) support of zero-overhead looping not only for innermost loops but also for arbitrarily nested loops. processors of such arrays are often limited in instruction memory size to reduce the area and power consumption. Hence, (3) we present methods for code compaction and code generation, and integrated these methods into a design tool. Finally, (4) we evaluated selected benchmarks by comparing our code generator with the Trimaran and VEX compiler frameworks. As the results show, our approach can reduce the size of the generated processor codes up to 64 % (Trimaran) and 55 % (VEX) while at the same time achieving a significant higher throughput.

关键词： massively parallel processor arrays Code generation Coarse-grained reconfigurable architectures Compilers Accelerators

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