DC/DC converters connected in series or parallel allow low power devices to be used in high power conversions. The input series output series (ISOS) connection is suitable for situations where both the input and outpu...
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DC/DC converters connected in series or parallel allow low power devices to be used in high power conversions. The input series output series (ISOS) connection is suitable for situations where both the input and output sides are high voltage fields. To ensure that each module shares voltage with the other, this paper proposes an active output voltage sharing (AOVS) control scheme. The scheme introduces sharing control in the output side so that the isolation is not needed between the input and output sides in the control loop. The AOVS control scheme, consisting of a common output voltage loop and individual output voltage sharing loop, has a master-slavestructure. To improve the reliability and realize a hot-plug, this paper also provides an automatic master-slave form of the AVOS control scheme. A simulation of the frequency and time domains is used to verify the accuracy of the small signal model, and an ISOS-connected prototype consisting of three forward converters is made to test the steady and dynamic characteristics of the proposed scheme.
Keeping distributed clocks closely synchronized is one of the basic requirements in wireless embedded applications. In the context of wireless applications, a clock synchronization protocol must tolerate message losse...
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ISBN:
(纸本)0769519377
Keeping distributed clocks closely synchronized is one of the basic requirements in wireless embedded applications. In the context of wireless applications, a clock synchronization protocol must tolerate message losses and should have a low communication overhead. The purpose of this paper is to present a clock synchronization protocol for distributed embedded systems in wireless environments. Our protocol adopts the master/slave structure based on a time transmission protocol and uses a drift correction algorithm for clock synchronization. The master node broadcasts synchronization messages through access point. The slave node estimates the master clock using the time transmission protocol and adjusts its virtual clock based on the continuous clock synchronization. Another advantage of the proposed protocol is that it uses a linear number of messages by transmitting one synchronization message in each resynchronization round and. tolerates message losses. The protocol is implemented and tested in a Windows NT and a WinCE. Its measurements indicate that the PC node and PDAs can be kept synchronized within the deviation bound of 8 milliseconds.
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