This paper presents a maximum a posterioriprobability (MAP) detector, based on a forward-only algorithm that can achieve high throughputs. The MAP algorithm is optimal in terms of bit error rate (BER) performance and...
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This paper presents a maximum a posterioriprobability (MAP) detector, based on a forward-only algorithm that can achieve high throughputs. The MAP algorithm is optimal in terms of bit error rate (BER) performance and, with Turbo processing, can approach performance close to the channel capacity limit. The implementation benefits from optimizations performed at both algorithm and circuit level. The proposed detector utilizes a deep-pipelined architecture implemented in skew-tolerant domino and experimentally measured results verify the detector can achieve throughputs greater than 750 Mb/s while consuming 2.4 W. The 16-state EEPR4 channel detector is implemented in a 0.13 mu m CMOS technology and has a core area of 7.1 mm(2).
This paper presents a maximum a posterioriprobability (MAP) detector, based on a forward-only algorithm that can achieve high throughputs. The MAP algorithm is optimal in terms of bit error rate (BER) performance and...
详细信息
ISBN:
(纸本)9781424407866
This paper presents a maximum a posterioriprobability (MAP) detector, based on a forward-only algorithm that can achieve high throughputs. The MAP algorithm is optimal in terms of bit error rate (BER) performance and, with Turbo processing, can approach performance close to the channel capacity limit. The implementation benefits from optimizations performed at both algorithm and circuit level. The proposed detector utilizes a deep-pipelined architecture implemented in skew-tolerant domino and experimentally measured results verify the detector can achieve throughputs greater than 750 Mb/s while consuming 2.4 W. The 16-state EEPR4 channel detector is implemented in a 0.13 mu m CMOS technology and has a core area of 7.1 mm(2).
A novel receiver architecture for the serial concatenation system of a convolutional code and a Gaussian minimum shift keying (GMSK) modulator is proposed. A maximum a pasteriori probabilityalgorithm for the multiple...
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A novel receiver architecture for the serial concatenation system of a convolutional code and a Gaussian minimum shift keying (GMSK) modulator is proposed. A maximum a pasteriori probabilityalgorithm for the multiple differential detection (MDD) of GMSK signals, which accepts a priori information and provides a soft-output for the subsequent convolutional decoder, is derived. The soft-output of the decoder is fed back to the MDD receiver for further improvement thus resulting in an iterative decoding structure.
Synchronisation is a requirement of all digital communication systems, while signal-to-noise ratio estimation is a particular requirement when using the maximum a posteriori probability algorithm for the iterative sta...
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Synchronisation is a requirement of all digital communication systems, while signal-to-noise ratio estimation is a particular requirement when using the maximum a posteriori probability algorithm for the iterative stage of a turbo code. The authors address these requirements and provide novel digital algorithms using the trellis structure of the component codes in a turbo code system. The results show that the algorithms provide the necessary functionality without degradation of performance and, as they are purely digital solutions, they are suitable for implementation on a digital signal processor or field programmable gate array.
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