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检索条件"主题词=memory based computing"

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ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable computing Fabric (Abstact Only) 16

ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Rec...

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Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

作者： Wenchao Qian Christopher Babecki Robert Karam Swarup Bhunia Case Western Reserve University Cleveland OH USA

ISBN: (纸本)9781450338561

Field Programmable Gate Arrays (FPGAs) are well-established as fine-grained hardware reconfigurable computing platforms. However, FPGA energy usage is dominated by programmable interconnects, which have poor scalability across different technology generations. In this work, we propose ENFIRE, a novel, energy-efficient, fine-grained, spatio-temporal, memory-based reconfigurable computing framework that provides the flexibility of bit-level information processing, which is not available in conventional coarse-grain reconfigurable architectures (CGRAs). A dense two-dimensional memory array is the main computing element in the proposed framework, which stores not only the data to be processed, but also the functional behavior of a mapped application in the form of lookup tables (LUTs) of various input/output sizes. Spatially distributed configurable computing elements (CEs) communicate with each other based on data dependencies using a mesh network, while execution inside each CE occurs in a temporal manner. A custom software framework has also been co-developed which enables application mapping to a set of CEs. By finding the right balance between spatial and temporal computing, it can achieve a highly energy-efficient mapping, significantly reducing the programmable interconnect overhead when compared with FPGA. Simulation results show an improvement of 7.6X in overall energy, 1.6X in energy efficiency, 1.1X in leakage energy, and 5.3X in Unified Energy-Efficiency, a metric that considers energy and area together, compared with comparable FPGA implementations for a set of random logic benchmarks.

关键词： energy-efficiency memory based computing spatio-temporal computing fine-grain reconfigurable hardware fpga

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MBARC: A Scalable memory based Reconfigurable computing Framework for Nanoscale Devices 08

MBARC: A Scalable Memory Based Reconfigurable Computing Fram...

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2008 Asia and South Pacific Design Automation Conference (ASP-DAC 2008), part 2

作者： Somnath Paul Swarup Bhunia Case Western Reserve University

ISBN: (纸本)9781424419227

While the emerging nanoscale devices show promises in terms of integration density and computing power, system design with these devices involve some major challenges, such as bottom-up design approach, effective integration with CMOS and defect tolerance. To address some of these challenges, we propose MBARC, a reconfigurable framework using memory as the primary computing element. The proposed framework leverages on the reported advantages of memory array design with nanodevices, which are compatible to fabrication into dense and regular structures. The main idea is to partition a logic circuit, implement the partitions as multi-input multi-output lookup tables in a memory array, and then use a simple CMOS-based scheduler to evaluate the partitions in topological time-multiplexed manner. Compared to existing reconfigurable nanocomputing models, the proposed memory based computing has three major advantages: 1) it minimizes the requirement of programmable interconnects, thus, saving design cost;2) it minimizes the number of CMOS interfacing elements (required for level restoration and cascading logic blocks);3) existing techniques for defect tolerance in memory array can be easily extended to this framework. Simulation results for a set of ISCAS benchmarks show average improvement of 32% in area, 21% in delay and 34% in energy per vector compared to nanoscale FPGA implementation.

关键词： Nanoscale Crossbar Reconfigurable architecture FPGA memory based computing

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