This paper presents architectures and implementation of a Sliding Memory Plane (SliM) Image processor to build a simd parallel computer. The paper also proposes an enhanced multiplication algorithm to reduce the gate ...
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This paper presents architectures and implementation of a Sliding Memory Plane (SliM) Image processor to build a simd parallel computer. The paper also proposes an enhanced multiplication algorithm to reduce the gate count and the number of cycles. The SliM chip consists of mesh-connected 5 x 5 PEs. Due to the idea of sliding, that is, overlapping the inter-PE communication time with the computation time, SliM can greatly reduce the inter-PE communication overhead. In addition, four operations corresponding to ALU, shift, delta I/O, and inter-PE communication can be grouped into an instruction to be executed in a cycle simultaneously. The implemented SliM chip operates at 25 MHz and gives 625 MIPS. Because of a mesh topology, a large number of chips can be easily connected to form a simd parallel computer. We have implemented the scalable SliM arrayprocessor and developed parallel algorithms for real-time image processing. (C) 1999 Academic Press.
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