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Sequential message-passing decoding of LDPC codes by partitioning check nodes

IEEE TRANSACTIONS ON COMMUNICATIONS 2008年第7期56卷 1025-1031页

作者： Kim, Sunghwan Jang, Min-Ho No, Jong-Seon Hong, Song-Nam Shin, Dong-Joon Seoul Natl Univ Dept Elect Engn & Comp Sci Seoul 151742 South Korea Hanyang Univ Dept Elect & Comp Engn Seoul 133791 South Korea

In this paper, we analyze the sequential message-passing decoding algorithm of low-density parity-check (LDPC) codes by partitioning check nodes. This decoding algorithm shows better bit error rate (BER) performance than the conventional message-passing decoding algorithm, especially for the small number of iterations. Analytical results indicate that as the number of partitioned subsets of check nodes increases, the BER performance is improved. We also derive the recursive equations for mean values of messages at check and variable nodes by using density evolution with a Gaussian approximation. From these equations, the mean values are obtained at each iteration of the sequential decoding algorithm and the corresponding BER values are calculated. They show that the sequential decoding algorithm converges faster than the conventional one. Finally, the analytical results are confirmed by the simulation results.

关键词： density evolution flooding schedule low-density parity-check (LDPC) codes message-passing decoding sequential decoding

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Efficient serial message-passing schedules for LDPC decoding

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IEEE TRANSACTIONS ON INFORMATION THEORY 2007年第11期53卷 4076-4091页

作者： Sharon, Eran Litsyn, Simon Goldberger, Jacob Tel Aviv Univ Sch Elect Engn IL-69978 Tel Aviv Israel Bar Ilan Univ Sch Engn IL-52900 Ramat Gan Israel

Conventionally, in each low-density parity-check (LDPC) decoding iteration all the variable nodes and subsequently all the check nodes send messages to their neighbors (flooding schedule). An alternative, more efficient, approach is to update the nodes' messages serially (serial schedule). A theoretical analysis of serial message passing decoding schedules is presented. In particular, the evolution of the computation tree under serial scheduling is analyzed. It shows that the tree grows twice as fast in comparison to the flooding schedule's one, indicating that the serial schedule propagates information twice as fast in the code's underlying graph. Furthermore, an asymptotic analysis of the serial schedule's convergence rate is done using the density evolution (DE) algorithm. Applied to various ensembles of LDPC codes, it shows that for long codes the serial schedule is expected to converge in half the number of iterations compared to the standard flooding schedule, when working near the ensemble's threshold. This observation is generally proved for the binary erasure channel (BEC) under some natural assumptions. Finally, an accompanying concentration theorem is proved.

关键词： belief propagation density evolution factor graph iterative decoding low-density parity-check (LDPC) codes message-passing decoding

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On the performance of high-rate TPC/SPC codes and LDPC codes over partial response channels

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IEEE TRANSACTIONS ON COMMUNICATIONS 2002年第5期50卷 723-734页

作者： Li, J Narayanan, KR Kurtas, E Georghiades, CN Texas A&M Univ Dept Elect Engn College Stn TX 77843 USA Seagate Res Seagate Technol Pittsburgh PA 15203 USA

This paper evaluates two-dimensional turbo product codes based on single-parity check codes (TPC/SPC) and low-density parity check (LDPC) codes for use in digital magnetic recording systems. It is first shown that the combination of a TPC/SPC code and a precoded partial response (PR) channel results in a good distance spectrum due to the interleaving gain. Then, density evolution is used to compute the thresholds for TPC/SPC codes and LDPC codes over PR channels. Analysis shows that TPC/SPC codes have a performance close to that of LDPC codes for large codeword lengths. Simulation results for practical block lengths show that TPC/SPC codes perform as well as LDPC codes in terms of bit error rate, but possess better burst error statistics which is important in the presence of an outer Reed-Solomon code. Further, the encoding complexity of TPC/SPC codes is only linear in the codeword length and the generator matrix does not have to be stored explicitly. Based on the results in the paper and these advantages, TPC/SPC codes seem like a viable alternative to LDPC codes.

关键词： data storage system density evolution iterative decoding low-density parity check codes message-passing decoding partial response channels precoding turbo product codes

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Deeply Pipelined Digit-Serial LDPC decoding

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2012年第12期59卷 2934-2944页

作者： Marshall, Philip A. Gaudet, Vincent C. Elliott, Duncan G. Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada Univ Waterloo Dept Elect & Comp Engn Waterloo ON N2L 3G1 Canada

Highly parallel VLSI implementations of low-density parity-check (LDPC) decoders have a large number of interconnections, which can result in designs with low logic density. Bit-serial architectures have been developed that reduce the number of wires needed, however, they do not fully realize the potential for deeply pipelined serial data processing. Digit-online arithmetic allows operations to be performed in a serial, digit-by-digit manner, making it ideal for use in implementing a digit-serial LDPC decoder. Digit-online circuits for the primitive operations required for an offset min-sum LDPC decoder are simple, and allow deep pipelining at the digit level. A new hardware architecture for LDPC decoding is demonstrated, using redundant number systems for the internal representation of values. We present post-layout decoder results for the (2048, 1723) 10GBASE-T LDPC code in a general-purpose 65 nm CMOS technology. The decoder requires a core area of 10.89 mm(2) and operates at a clock frequency of 980 MHz. The decoder can simultaneously decode two 4-bit frames at 41.8 Gbit/s or one 10-bit frame at 20.9 Gbit/s.

关键词： Forward error control (FEC) iterative decoder architecture low-density parity-check (LDPC) codes message-passing decoding

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On the Design of Fast Convergent LDPC Codes for the BEC: An Optimization Approach

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IEEE TRANSACTIONS ON COMMUNICATIONS 2015年第2期63卷 351-363页

作者： Jamali, Vahid Karimian, Yasser Huber, Johannes Attari, Mahmoud Ahmadian Univ Erlangen Nurnberg Inst Digital Commun D-91054 Erlangen Germany KN Toosi Univ Technol KNTU Dept Commun Tehran 19697 Iran Univ Erlangen Nurnberg Inst Informat Transmiss D-91054 Erlangen Germany

The complexity-performance trade-off is a fundamental aspect of the design of low-density parity-check (LDPC) codes. In this paper, we consider LDPC codes for the binary erasure channel (BEC), use code rate for performance metric, and number of decoding iterations to achieve a certain residual erasure probability for complexity metric. We first propose a quite accurate approximation of the number of iterations for the BEC. Moreover, a simple but efficient utility function corresponding to the number of iterations is developed. Using the aforementioned approximation and the utility function, two optimization problems w.r.t. complexity are formulated to find the code degree distributions. We show that both optimization problems are convex. In particular, the problem with the proposed approximation belongs to the class of semi-infinite problems which are computationally challenging to be solved. However, the problem with the proposed utility function falls into the class of semi-definite programming (SDP) and thus, the global solution can be found efficiently using available SDP solvers. Numerical results reveal the superiority of the proposed code design compared to existing code designs from literature.

关键词： Low-density parity-check (LDPC) codes complexity-performance trade-off density evolution message-passing decoding semi-definite programming (SDP)

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Implementation aspects of LDPC convolutional codes

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IEEE TRANSACTIONS ON COMMUNICATIONS 2008年第7期56卷 1060-1069页

作者： Pusane, Ali Emre Feltstroem, Alberto Jimnez Sridharan, Arvind Lentmaier, Michael Zigangirov, Kamil Sh. Costello, Daniel J., Jr. Univ Notre Dame Dept Elect Engn Notre Dame IN 46556 USA DS2 Design Syst Silicon Valencia Spain

Potentially large storage requirements and long initial decoding delays are two practical issues related to the decoding of low-density parity-check (LDPC) convolutional codes using a continuous pipeline decoder architecture. In this paper, we propose several reduced complexity decoding strategies to lessen the storage requirements and the initial decoding delay without significant loss in performance. We also provide bit error rate comparisons of LDPC block and LDPC convolutional codes under equal processor (hardware) complexity and equal decoding delay assumptions. A partial syndrome encoder realization for LDPC convolutional codes is also proposed and analyzed. We construct terminated LDPC convolutional codes that are suitable for block transmission over a wide range of frame lengths. Simulation results show that, for terminated LDPC convolutional codes of sufficiently large memory, performance can be improved by increasing the density of the syndrome former matrix.

关键词： low-density parity-check codes convolutional codes iterative decoding message-passing decoding decoder implementation

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Importance sampling for Tanner trees

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IEEE TRANSACTIONS ON INFORMATION THEORY 2005年第6期51卷 2183-2189页

作者： Xia, B Ryan, WE Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

This correspondence presents an importance sampling (IS) simulation scheme for the soft iterative decoding on loop-free multiple-layer trees. It is shown that this scheme is asymptotically efficient in that, for an arbitrary tree and a given estimation precision, the required number of samples is inversely proportional to the noise standard deviation. This work has its application in the simulation of low-density parity-check (LDPC) codes.

关键词： importance sampling low-density parity-check (LDPC) code message-passing decoding Tanner graph Tanner tree

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Design of LDPC Decoders for Improved Low Error Rate Performance: Quantization and Algorithm Choices

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IEEE TRANSACTIONS ON COMMUNICATIONS 2009年第11期57卷 3258-3268页

作者： Zhang, Zhengya Dolecek, Lara Nikolic, Borivoje Anantharam, Venkat Wainwright, Martin J. Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90095 USA

Many classes of high-performance low-density parity-check (LDPC) codes are based on parity check matrices composed of permutation submatrices. We describe the design of a parallel-serial decoder architecture that can be used to map any LDPC code with such a structure to a hardware emulation platform. High-throughput emulation allows for the exploration of the low bit-error rate (BER) region and provides statistics of the error traces, which illuminate the causes of the error floors of the (2048, 1723) Reed-Solomon based LDPC (RS-LDPC) code and the (2209, 1978) array-based LDPC code. Two classes of error events are observed: oscillatory behavior and convergence to a class of non-codewords, termed absorbing sets. The influence of absorbing sets can be exacerbated by message quantization and decoder implementation. In particular, quantization and the log-tanh function approximation in sum-product decoders strongly affect which absorbing sets dominate in the error-floor region. We show that conventional sum-product decoder implementations of the (2209, 1978) array-based LDPC code allow low-weight absorbing sets to have a strong effect, and, as a result, elevate the error floor. Dually-quantized sum-product decoders and approximate sum-product decoders alleviate the effects of low-weight absorbing sets, thereby lowering the error floor.

关键词： Low-density parity-check (LDPC) code message-passing decoding iterative decoder implementation error floor absorbing set

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A Finite-Length Algorithm for LDPC Codes Without Repeated Edges on the Binary Erasure Channel

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IEEE TRANSACTIONS ON INFORMATION THEORY 2009年第1期55卷 27-32页

作者： Johnson, Sarah J. Univ Newcastle Sch Elect Engn & Comp Sci Callaghan NSW 2308 Australia

This paper considers the performance, on the binary erasure channel, of low-density parity-check (LDPC) codes without repeated edges in their Tanner graphs. A modification to existing finite-length analysis algorithms... 详细信息

关键词： Binary erasure channels finite-length analysis iterative decoding low-density parity-check (LDPC) codes message-passing decoding

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On the performance of turbo product codes over partial response channels

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IEEE TRANSACTIONS ON MAGNETICS 2001年第4期37卷 1932-1934页

作者： Li, J Kurtas, E Narayanan, KR Georghiades, CN Texas A&M Univ Dept Elect Engn College Stn TX 77843 USA Seagate Res Seagate Technol Pittsburgh PA 15203 USA

This paper evaluates the performance of single-parity check turbo product codes (TPC/SPC) over partial response channels. A rate-0.94 and a rate-0.89 TPC/SPC code are considered for use with PR4/EPR4 channels with proper precoding and with turbo equalization. Gains of 4.5 to 5 dB are obtained at BER of 10(-5), revealing performance comparable to that of low density parity check codes. Apart from its linear encoding/decoding complexity and highly parallelizable decoding algorithm, TPC/SPC codes demonstrate favorable error statistics which are in harmony with the outer Reed-Solomon error correction code (RS-ECC), indicating it to be a promising candidate for future recording systems.

关键词： data storage system iterative decoding message-passing decoding partial response channels precoding turbo product codes

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