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检索条件"主题词=microprocessor logic circuit"

共 40 条记录，以下是11-20 订阅

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Optimized Degree Distributions for Binary and Non-Binary LDPC Codes in Flash Memory

Optimized Degree Distributions for Binary and Non-Binary LDP...

引用

International Symposium on Information Theory and its Applications (ISITA)

作者： Vakilinia, Kasra Divsalar, Dariush Wesel, Richard D. Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90095 USA CALTECH Jet Prop Lab Pasadena CA 91109 USA

ISBN: (纸本)9784885522925

This paper uses extrinsic-information-transfer (EXIT)-function analysis employing the reciprocal channel approximation (RCA) to obtain optimal LDPC code degree distributions for initial hard decoding (one-bit quantization of the channel output) and for decoding with the soft information provided by additional reads in both SLC (two-level cell) and MLC (four-level-cell) Flash memory. These results indicate that design for hard decoding can provide irregular degree distributions that have good thresholds across the range of possible decoding precisions. These results also quantify the potential benefit of irregular LDPC codes as compared to regular LDPC codes in the flash setting and compare the RCA-EXIT thresholds of word-line voltages optimized for maximum mutual information (MMI) and word-line voltages that explicitly minimize the RCA-EXIT threshold of a specific LDPC degree distribution. Along the way, this paper illustrates that the MMI optimization of word-line voltages for five reads is a quasi-convex problem for the Gaussian model of SLC Flash. The paper also uses RCA-based EXIT analysis to show that for the same spectral efficiency of 0.9 bits per cell, rate-0.45 non-binary LDPC codes on MLC Flash systems provide thresholds more than 0.5 dB better than rate-0.9 binary LDPC codes on SLC Flash with the same number of reads (i.e. three reads that would provide hard decisions for MLC and limited soft information for SLC). The MLC approach has a potential threshold improvement of more than 1.5 dB over the SLC approach when both systems have access to the full soft information.

关键词： Approximation methods Decoding Mutual information Optimization Parity check codes Quantization (signal) Threshold voltage CCL21 gene microprocessor logic circuit DECODING STANFORD LINEAR COLLIDER DETECTOR flash memories threshold voltage MLC1 gene Flashing low density parity check codes Approximation method parity check codes Line voltage

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Short-SET: An Energy-Efficient Write Scheme for MLC PCM

Short-SET: An Energy-Efficient Write Scheme for MLC PCM

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IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)

作者： Li, Bing Hu, Yu Li, Xiaowei Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing 100864 Peoples R China Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9781479955763

Phase change memory (PCM) has many advantages over the traditional DRAM technology, hence it becomes a promising candidate for main memory. Multi-level cell (MLC) PCM has the benefits of higher capacity and lower cost-per-bit due to store multiple bits in a single cell. However, MLC PCM employs an iterative write scheme, which is precise, reliable but slow, incurring adverse impact on the system performance. In this work, we analyzed the characteristics of the SET pulse in PCM, and modeled the relationship of the resistance and the SET pulse in MLC. Based on the analysis, we proposed a short SET pulse as an iterative pulse for MLC, so as to accelerate the MLC PCM write operation without the reliability degradation. Experimental results show that the Short-SET write scheme could effectively alleviate the long write problem of MLC PCM and improve the system performanceby 90%. Meanwhile, the write power is reduced by 23%.

关键词： Acceleration Phase change materials Random access memory Reliability Resistance System performance System performance microprocessor logic circuit MLC1 gene Pulse code modulation random access machine Phase change materials acceleration

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On Codes Correcting Bidirectional Limited-Magnitude Errors for Flash Memories

On Codes Correcting Bidirectional Limited-Magnitude Errors f...

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International Symposium on Information Theory and its Applications (ISITA)

作者： Jeon, Myeongwoon Lee, Jungwoo Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul 151744 South Korea

ISBN: (纸本)9784885522673

NAND multi-level cell (MLC) flash memories are widely used due to low cost and high capacity. However, the increased number of levels in MLC results in larger interference and errors. The errors in MLC flash memories tend to be directional and limited-magnitude. Many related works focus on asymmetric errors, but bidirectional errors also occur because of the bidirectional interference and the adjustment of the hard-decision reference voltages. To take advantage of the characteristics, we propose t bidirectional (l(u), l(d)) limited-magnitude error correction codes, which can reduce errors more effectively. The proposed code is systematic, and can correct t bidirectional errors with upward and downward magnitude of l(u) and l(d), respectively. The proposed method is advantageous in that the parity size is reduced, and the error rate performance is better than conventional error correction codes when the code rate is equal.

关键词： flash memories Error correction codes code rate Bidirectional microprocessor logic circuit MLC1 gene amplitude error Lutetium bit error rate performance DIRECTIONAL

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Tomographic Cherenkov-excited luminescence scanned imaging based on back-projection reconstruction demonstrates 0.3mm spatial resolution for molecular reporter through 2-3cm of tissue 5

Tomographic Cherenkov-excited luminescence scanned imaging b...

引用

Conference on Molecular-Guided Surgery - Molecules, Devices, and Applications V

作者： Jia, Mengyu Cao, Xu Gunn, Jason R. Bruza, Petr Jiang, Shudong Pogue, Brian W. Dartmouth Coll Thayer Sch Engn Hanover NH 03755 USA

ISBN: (数字)9781510623675

ISBN: (纸本)9781510623668;9781510623675

Cherenkov-excited luminescence scanned imaging (CELSI) is achieved with External Beam Radiotherapy, to map out molecular luminescence intensity or lifetime in tissue. In order to realize a deeper imaging depth with a reasonable spatial resolution, we optimized the original scanning gesture to do in a similar way to computed tomography (CT) and the image reconstruction was instead used a customized Maximum-likelihood expectation maximization (ML-EM) for CELSI. In tomographic CELSI (TCELSI), tomographic images are generated by irradiating the subject using a sequence of programmed X-ray beams at a fixed projection angle, while sensitive measurement is to take a sum for all image pixels from an intensified charge-coupled device. By restricting the X-ray excitation to a single, narrow beam of radiation, the origin of the optical photons can be inferred regardless of where these photons were detected, and how many times they scattered in tissue. Measurement geometry was designed for clinical expectation: CT scanning was achieved by a clinical linear accelerator (LINAC), where X-ray beam sequence and multiple projections were realized with multi leaf collimator (MLC) and gantry movement, respectively. Furthermore, in most modern External Beam Radiotherapy, MLC movement is synchronized with gantry angle to release a uniform radiation, and some of treatment plans, e.g., Intensity Modulated Radiation Therapy (IMRT), have a potential to match the scanning way mentioned. By including Cherenkov imaging results, medium surface profile can be additionally acquired, which can be used as boundary reference to do depth correction and co-register with molecular images. Resolution phantom studies showed that a 0.3 mm diameter capillary tube containing 0.01 nM luminescent nanospheres could be recognized at a depth of 21 mm into tissue-like media. Small animal imaging with a 1 mm diameter cylindrical target demonstrated that fast 3D data acquisition was achieved by a multi-pinhole colli

关键词： teletherapy 3D data acquisition Tomography image reconstruction depth correction Imaging luminescence Charge coupled devices Photon surface topography microprocessor logic circuit collimators MLC1 gene

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TriState-SET: Proactive SET for Improved Performance of MLC Phase Change Memories 33

TriState-SET: Proactive SET for Improved Performance of MLC ...

引用

33rd IEEE International Conference on Computer Design (ICCD)

作者： Zhang, Xianwei Zhang, Youtao Yang, Jun Univ Pittsburgh Dept Comp Sci Pittsburgh PA 15260 USA Univ Pittsburgh Elect & Comp Engn Dept Pittsburgh PA USA

ISBN: (纸本)9781467371667

The emerging Phase Change Memory (PCM) has many advantages such as good scalability and low leakage. MLC (Multi-Level Cell) PCM further extends the benefits by storing two or more bits per cell and thus reducing the per bit cost. However, adopting MLC PCM in main memory often leads to long write latency, high energy consumption, and degraded performance. In this paper, we propose TriState-SET, a proactive-SET based write strategy for improving MLC PCM write performance. TriState-SET proactively places device cells of a dirty memory line in full SET state. By utilizing only three states of 2-bit MLC PCM, TriState-SET involves only fast state transitions when writing such a line at write-back time. Our experimental results show that TriState-SET increases performance by 11% and saves system energy by 6.7% (up to 12.2%), while achieving up to 25% (average 14.1%) energy-delay-product improvement.

关键词： Encoding Memory management Performance evaluation Phase change materials Phase change memory Resistance Writing Phase change memory Writing Store management Phase change materials microprocessor logic circuit MLC1 gene Performance Evaluation Pulse code modulation degraded performance main memory

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Improving Min-sum LDPC Decoding Throughput by Exploiting Intra-cell Bit Error Characteristic in MLC NAND Flash Memory

Improving Min-sum LDPC Decoding Throughput by Exploiting Int...

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30th Symposium on Mass Storage Systems and Technologies (MSST)

作者： Zhao, Wenzhe Sun, Hongbin Lv, Minjie Dong, Guiqiang Zheng, Nanning Zhang, Tong Xi An Jiao Tong Univ Inst AI&R Xian Peoples R China Skyera Inc San Jose CA USA Rensselaer Polytech Inst ECSE Dept Rensselaer NY USA

ISBN: (纸本)9781479956715

Multi-level per cell (MLC) technique significantly improves storage density, but also poses new challenge to data integrity in NAND flash memory. Therefore, low-density parity-check (LDPC) code and soft-decision memory sensing have become indispensable in future NAND flash-based solid state drive design. However, these more powerful technologies inevitably increase the memory read latency and hence degrade the decoding throughput. Motivated by intra-cell unbalanced bit error probability and data dependency in MLC NAND flash memory, this paper proposes two techniques, i.e. intra-cell data placement interleaving and intra-cell data dependency aware min-sum decoding, to effectively improve the throughput of LDPC decoding. Experimental results show that, the proposed techniques used in an integrated way can improve the LDPC decoding throughput by up to 85% when the MLC NAND flash chip is heavily cycled, compared with conventional design practice.

关键词： Ash Decoding Error probability Parity check codes Sensors Threshold voltage Throughput DECODING Throughput flash memories parity check codes Error probability threshold voltage low density parity check codes Ashes Sensors microprocessor logic circuit MLC1 gene data dependency Storage density

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Multilevel Codes for Satellite Broadcasting under LMS Channels

Multilevel Codes for Satellite Broadcasting under LMS Channe...

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IEEE 72nd Vehicular Technology Conference Fall 2010

作者： Vargas, Aharon Gerstacker, Wolfgang H. Breiling, Marco Heuberger, Albert Fraunhofer Inst Integrated Circuits IIS Wolfsmantel 33 D-91058 Erlangen Germany Univ Erlangen Nurnberg Chair Mobile Commun D-91058 Erlangen Germany Tech Univ Ilmenau Fachgebiet Digitaler Rundfunk D-98693 Ilmenau Germany

ISBN: (纸本)9781424435746

In this paper, we evaluate a multilevel coding (MLC) scheme with multi-stage decoding (MSD) designed for satellite broadcasting communications, where services with different quality of service (QoS) are desirable. A simple Land-Mobile-Satellite (LMS) channel model is presented, based on channel states and their transitions. The instantaneous channel capacity for suburban and forest scenarios is calculated using the mutual information concept. An established transmission scheme for satellite broadcasting, which uses bit-interleaved coded modulation (BICM) with Gray mapping, is compared with the MLC scheme in terms of channel capacity and outage probability. The effect of removing a long channel interleaver in the physical layer is analyzed, showing that the MLC scheme is a good alternative to BICM for satellite broadcasting.

关键词： Satellite broadcasting Levamisole learning management system Multilevel coding Channel capacity microprocessor logic circuit MLC1 gene Physical layer

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A reliability enhancement mechanism for high-assurance MLC flash-based storage systems

A reliability enhancement mechanism for high-assurance MLC f...

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1st International Workshop on Cyber-Physical Systems, Networks, and Applications (CPSNA) held during 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

作者： Mir, Irfan F. McEwan, Alistair A. Univ Leicester Dept Engn Leicester LE1 7RH Leics England

ISBN: (纸本)9780769545028

Solid State Devices (SDDs) are replacing mechanical data storage devices such as Hard Disk Drives (HDDs). On the other hand the data reliability in these systems is being questioned due to the fast growth in flash technology such as Multi-Level Cell (MLC). Recently it has been revealed that the Bit Error Rate (BER) increases exponentially in MLC flash memories as they experience more flash writes. Additionally RAID in flash-based storage systems has an inherent problem, that all flash devices should not reach end of life at the same time. Diff-RAID [2] overcomes the said problem. However, Diff-RAID mechanism suffers from drastic age-variation especially during the first few replacements, a problem that has been identified and addressed in this research. A new reliability enhancement mechanism for high-assurance MLC flash-based storage systems has been proposed here, and is compared with published Diff-RAID results. Our mechanism has shown promising results. In terms of convergence, the proposed scheme is 7 times faster. Furthermore, no single device crosses 66% of the age (i.e. max. erasure cycles), unlike the Diff-RAID where in the first few replacements, few devices reach 70-80% of age, which is great improvement in terms of data reliability.

关键词： BER Data reliability NAND flash RAID SSD high-assurance storage Bit error rate Cache Memory System flash memories RAID solid-state disk Silver Sulfadiazine microprocessor logic circuit MLC1 gene Ziziphus mauritiana Flashing

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STT-RAM Reliability Enhancement through ECC and Access Scheme Optimization

STT-RAM Reliability Enhancement through ECC and Access Schem...

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18th IEEE International Symposium on Consumer Electronics (ISCE)

作者： Wen, Wujie Zhang, Yaojun Mao, Mengjie Chen, Yiran Univ Pittsburgh Dept Elect & Comp Engn Pittsburgh PA 15260 USA

ISBN: (纸本)9781479945917

Multi-level cell Spin-Transfer Torque RAM (MLC STT-RAM) greatly suffers from the significantly degraded operation reliability and high programming cost. In this paper, a novel MLC design, namely ternary-state MLC (TS-MLC STT-RAM), is proposed for high-reliable high-performance memory systems by leveraging a cross-layer solution set. Based on the structure, several circuit and architecture schemes are proposed to enhance both the reliability and access latency of the memory cells.

关键词： Computer architecture Error analysis microprocessors Programming Random access memory Reliability Resistance random access machine macroprocessor Computer Architecture Programming Error analysis EMERGENCY CONTROL CENTERS Error correction codes Elliptic curve cryptography immunocytes microprocessor logic circuit MLC1 gene

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Improving Write Operations in MLC Phase Change Memory

Improving Write Operations in MLC Phase Change Memory

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18th IEEE International Symposium on High-Performance Computer Architecture (HPCA)

作者： Jiang, Lei Zhao, Bo Zhang, Youtao Yang, Jun Childers, Bruce R. Univ Pittsburgh Dept Elect & Comp Engn Pittsburgh PA 15260 USA Univ Pittsburgh Dept Comp Sci Pittsburgh PA USA

ISBN: (纸本)9781467308243;9781467308267

Phase change memory (PCM) recently has emerged as a promising technology to meet the fast growing demand for large capacity memory in modern computer systems. In particular, multi-level cell (MLC) PCM that stores multiple bits in a single cell, offers high density with low per-byte fabrication cost. However, despite many advantages, such as good scalability and low leakage, PCM suffers from exceptionally slow write operations, which makes it challenging to be integrated in the memory hiearchy. In this paper, we propose architectural innovations to improve the access time of MLC PCM. Due to cell process variation, composition fluctuation and the relatively small differences among resistance levels, MLC PCM typically employs an iterative write scheme to achieve precise control, which suffers from large write access latency. To address this issue, we propose write truncation (WT) to reduce the number of write iterations with the assistance of an extra error correction code (ECC). We also propose form switch (FS) to reduce the storage overhead of the ECC. By storing highly compressible lines in SLC form, FS improves read latency as well. Our experimental results show that WT and FS improve the effective write/read latency by 57%/28% respectively, and achieve 26%performance improvement over the state of the art.

关键词： write operation microprocessor logic circuit MLC1 gene Error correction codes Pulse code modulation Storage access times Computer systems Phase change memory Elliptic curve cryptography EMERGENCY CONTROL CENTERS accuracy control performance boost Latency capacitor storage

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