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54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Kabylkas, Nursultan Thorn, Tommy Srinath, Shreesha Xekalakis, Polychronis Renau, Jose UC Santa Cruz Santa Cruz CA 95064 USA Esperanto Technol Mountain View CA USA Intel Portland OR USA Nvidia Portland OR USA

ISBN: (纸本)9781450385572

The study on verification trends in the semiconductor industry shows that the design complexity is increasing, fewer companies achieve first silicon success and need more spins before production, companies hire more verification engineers, and 53% of the whole hardware-design-cycle is spent on the design verification [18]. The cost of a respin is high, and more than 40% of the cases that contribute to it are post-fabrication functional bug exposures [16]. The study also shows that 65% of verification engineers' time is spent on debug, test creation, and simulation [17]. This paper presents a set of tools for RISC-V processor verification engineers that help to expose more bugs before production and increase the productivity of time spent on debugging, test creation and simulation. We present Logic Fuzzer (LF), a novel tool that expands the verification space exploration without the creation of additional verification tests. The LF randomizes the states or control signals of the design-under-test at the places that do not affect functionality. It brings the processor execution outside its normal flow to increase the number of microarchitectural states exercised by the tests. We also present Dromajo, the state of the art processor verification framework for RISC-V cores. Dromajo is an RV64GC emulator that was designed specifically for co-simulation purposes. It can boot Linux, handle external stimuli, such as interrupts and debug requests on the fly, and can be integrated into existing testbench infrastructure with minimal effort. We evaluate the effectiveness of the tools on three RISC-V cores: CVA6, BlackParrot, and BOOM. Dromajo by itself found a total of nine bugs. The enhancement of Dromajo with the Logic Fuzzer increases the exposed bug count to thirteen without creating additional verification tests.

关键词： microprocessor verification co-simulation enhanced simulation RISC-V

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Balancing Automation and Control for Formal verification of microprocessors 33rd

Balancing Automation and Control for Formal Verification of ...

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33rd International Conference on Computer-Aided verification (CAV)

作者： Goel, Shilpi Slobodova, Anna Sumners, Rob Swords, Sol Centaur Technol Inc Austin TX 78731 USA

ISBN: (纸本)9783030816858;9783030816841

Formal methods are becoming an indispensable part of the design process in software and hardware industry. It takes robust tools and proofs to make formal validation of large scale projects reliable. In this paper, we will describe the current status of formal verification at Centaur Technology. We will explain our challenges and our methodology how various proofs and verification artifacts are interconnected and how we keep them consistent over the duration of a project. We also describe our main engine a powerful symbolic simulator with rewriting capabilities that is integrated in a theorem prover and proven correct.

关键词： Hardware verification microprocessor verification Microcode verification Formal methods ACL2 Symbolic simulation Decision procedures

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Syntactically Controlled Generation of the Test Programs for microprocessor verification

Syntactically Controlled Generation of the Test Programs for...

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第二届国际测量仪器与测试自动化学术会议

作者： Ghennady Bodean Diana Bodean Serghei Borshevich Designing and Manufacture Electronic Apparatuses Dep.Radio-electronics and Telecommunication Faculty Technical University TUM KishinauR.Moldova Computer Science and Technology School of Information Renmin University Beijing

This paper presents an approach to synthesis of stylistically and syntactically controlled generator of the microprocessor test *** dependence of test length of the confidence level and the probabilities repartition of coverage metric is *** procedure of synthesis of a test program generator is developed,represented by a stochastic grammar for a known *** performed test experiments clearly demonstrate the advantages of the proposed syntactic approach in comparison with other competitive methods of generation stimuli for verification of microprocessors

关键词： test program microprocessor verification constrained-random generation

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verification-Purpose Operating System for microprocessor System-Level Functions

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IEEE DESIGN & TEST OF COMPUTERS 2010年第1期27卷 76-84页

作者： Gong, Lingkan Lu, Jingfen E China Inst Comp Technol Dept IC Design Shanghai 200233 Peoples R China

microprocessor system-level functions that provide hardware support for software are difficult to verify on FPGA prototypes. Traditional FPGA verification involves running a general-purpose operating system such as Linux. However, such a GPOS is difficult to control, and debug is inefficient. The verification-Purpose Operating System, on the other hand, simplifies debug and is easy to control. VPOS also significantly increases coverage over that of GPOS approaches.

关键词： Design And Test FPGA microprocessor verification System Level Function verification Purpose Operating System VPOS

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Feedback-Based Coverage Directed Test Generation: An Industrial Evaluation

Feedback-Based Coverage Directed Test Generation: An Industr...

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6th Haifa verification Conference

作者： Ioannides, Charalambos Barrett, Geoff Eder, Kerstin Univ Bristol Ind Doctorate Ctr Syst Queens Bldg Bristol BS8 1TR Avon England Broadcom Corp Broadcom BBE BU Bristol BS16 1FJ Avon England Univ Bristol Dept Comp Sci Bristol BS8 1UB Avon England

ISBN: (纸本)9783642195822

Although there are quite a few approaches to Coverage Directed test Generation aided by Machine Learning which have been applied successfully to small and medium size digital designs, it is not clear how they would scale on more elaborate industrial-level designs. This paper evaluates one of these techniques, called MicroGP, on a fully fledged industrial design. The results indicate relative success evidenced by a good level of code coverage achieved with reasonably compact tests when compared to traditional test generation approaches. However, there is scope for improvement especially with respect to the diversity of the tests evolved.

关键词： microprocessor verification Coverage Directed Test Generation Genetic Programming MicroGP

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Automatic verification of external interrupt behaviors for microprocessor design

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2008年第9期27卷 1670-1683页

作者： Yang, Fu-Ching Huang, Wen-Kai Zhong, Jing-Kun Huang, Ing-Jer Natl Sun Yat Sen Univ Dept Comp Sci & Engn Kaohsiung 804 Taiwan

Interrupt behaviors, particularly the external ones, are difficult to verify in a microprocessor. Because the external interrupt arrival time and the microprocessor response time must be precise, verification requires sophisticated hardware and software design. This paper proposes a computer-aided design tool, called processor exception verification tool (PEVT), to verify the external interrupt behaviors of microprocessors, including individual, multiple, and nested interrupts. An architecture description language extension, called Exception Description Language (EXPDL), is developed for the designer to capture the external interrupt behaviors for the microprocessor under verification. PEVT is responsible for generating the verification cases, consisting of both the hardware and software modules, which are then used to trigger the expected behaviors. A monitor is also generated from the EXPDL description to verify these cases. PEVT has been applied to the verification of an academic implementation of the ARM7 microprocessor core and a public domain scalable processor architecture (SPARC) microprocessor core. The ARM7 has had a system-on-a-chip test chip and software porting including multimedia applications (MP3/JPEG/...) and a real time operating system mu C-OSII. PEVT successfully identified several sophisticated remaining bugs with 527 lines of EXPDL description and took only 4 204 961 cycles of register transfer language simulation with execution time of 4.5 h in a SUN Blade2000 workstation. The experiment shows that PEVT could generate highly focused verification cases, less than 98 cycles per case on the average, which identify potential bugs with much less simulation cycles at the early verification stage, compared with traditional manual-based approaches.

关键词： architecture description language (ADL) dynamic assertion based external interrupt verification microprocessor verification monitor simulation based trigger

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Automatic formal verification of control logic in hardware designs

Automatic formal verification of control logic in hardware d...

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作者： Andraus, Zaher S. University of Michigan

学位级别：Ph.D.

Our work addresses the challenge of scaling pre-silicon functional verification of hardware designs such as microprocessors and microcontrollers. These designs employ wide datapaths with arithmetic, logical, and memory units, and complex control logic that coordinates their functionality. This overall complexity results in an enormous state space with vast room for design errors, and prevents designers from being able to comprehensively reason about the correctness of digital systems deployed in numerous devices, whose failure causes serious losses, monetary and otherwise. In particular, control optimizations play a global role in coordinating the functionality and data flow. This makes them extremely error-prone and harder to verify locally. To remedy that, a design implementation can be verified against its full specification model which has a much simpler control logic. Then, a formal proof of equivalence exhaustively checks the state space for potential control bugs, or proves the lack thereof. Contrary to simulation-based approaches, which compromises completeness for speed, formal equivalence is hindered by the exponential state explosion. To overcome that, previous approaches abstract datapath components away in order to eliminate the complexity introduced by them, and to gear the verification towards the control logic. Due to the loose separation between datapath and control in most designs and hardware description languages, naïve abstraction results in compromising the accuracy of the verification, and in generating spurious behavior that does not exist in the original design, or masking real behavior from being represented in the abstract model. Our work presents a systematic and fully automatic abstraction-based method to overcome these issues. A sound abstraction to fragments of first-order logic is coupled with refinement mechanisms that adjust the abstract model and prevent false alarms arising due to spurious behavior. Our approach includes novel tec

关键词： microprocessor verification Counterexample-Guided Abstraction Refinement Thesis

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Automatic functional test program generation for microprocessor verification 05

Automatic functional test program generation for microproces...

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10th Asia and South Pacific Design Automation Conference

作者： Li, Tun Zhu, Dan Liang, Lei Guo, Yang Li, SiKun Natl Univ Def Technol Hunan Peoples R China

ISBN: (纸本)0780387368

A novel specification driven and constraints- solving based method to automatically generate test programs from simple to complex ones for advanced microprocessors is presented in this paper: Our microprocessor architectural automatic test program generator (MA(2)TG) can produce not only random test programs but also a sequence of instructions for a specific constraint by specifying a user constraints file. The proposed methodology makes three important contributions. First, it simplifies the microprocessor architecture modeling and eases adoption of architecture modification via architecture description language (ADL) specification. Second, it generates test programs for specific constraints utilizing the power of state-to-art constraints solving techniques. Finally, the number of test program for microprocessor verification and the verification time are dramatically reduced. We applied this method on DLX processor to illustrate the usefulness of our approach.

关键词： microprocessor chips automatic test pattern generation formal verification constraint handling automatic functional test program generation microprocessor verification specification driven constraints solving technique microprocessor architectural automatic test program generator random test programs user constraints file microprocessor architecture modeling architecture modification architecture description language verification time reduction DLX processor

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Invited Tutorial: Considerations in the Design and verification of microprocessors for Safety-Critical and Security-Critical Applications

Invited Tutorial: Considerations in the Design and Verificat...

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8th International Conference on Formal Methods in Computer-Aided Design

作者： Hardin, David S. Rockwell Collins Inc Adv Technol Ctr Cedar Rapids IA USA

ISBN: (纸本)9781424427352

In this tutorial, we will examine issues in the design and verification of microprocessors for safety-critical and security-critical applications. We will consider architectural and design alternatives to support high-assurance applications, and will describe techniques to improve secure system evaluation -- measured in terms of completeness, human effort required, time, and cost -- through the use of highly automated formal methods. We will describe practical techniques for creating executable formal computing platform models that can both be proved correct, and also function as high-speed simulators. This allows us to both verify the correctness of the models, as well as validate that the formalizations accurately model what was actually designed and built. As a case study, we will examine the design and verification of the Rockwell Collins AAMP7G microprocessor. The AAMP7G, currently in use in Rockwell Collins high-assurance system products, supports strict time and space partitioning in hardware, and has received an NSA MILS (Multiple Independent Levels of Security) certificate based in part on proofs of correctness. We will discuss the AAMP7G verification effort, focusing on the proof architecture that enabled us to show that the AAMP7G separation kernel microcode implements a particular security specification, using the ACL2 theorem prover.

关键词： microprocessor verification theorem proving partitioning ACL2

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Approaches for monitoring vectors on microprocessor buses

Approaches for monitoring vectors on microprocessor buses

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Internation Conference on Embedded Systems and Applications/International Conference on VLSI

作者： Arteaga, H Al-Asaad, H Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

ISBN: (纸本)1932415416

This paper introduces two new method for observing and recording the vectors that have been asserted on a bus. The first is a software approach that uses a novel data structure similar to binary decision diagrams which allows for a compact representation of stored values. Even though the new data structure presented in this paper can potentially grow to contain just as many nodes as there are possible values, such cases are often rare. The second is a hardware approach that is based on a simple circuit consisting of a small memory and two counters and has the ability to perform at the speed of the microprocessor.

关键词： design validation bus monitoring microprocessor verification post-silicon debug

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