IEEE Computer Society (CS) technical communities (TCs) are the foundry from which all our technical conferences are built and run. Our TCs attract all kinds of people in the field who come together to plan events, ser...
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IEEE Computer Society (CS) technical communities (TCs) are the foundry from which all our technical conferences are built and run. Our TCs attract all kinds of people in the field who come together to plan events, serve volunteer leadership roles, and help define the features and future of these technical spaces.
Our educational project has three primary goals. First, we want to provide a robust vision of how hardware and software interplay, by integrating the design of an instruction set (through microprogramming) and using t...
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Our educational project has three primary goals. First, we want to provide a robust vision of how hardware and software interplay, by integrating the design of an instruction set (through microprogramming) and using that instruction set for assembly programming. Second, we wish to offer a versatile and interactive tool where the previous integrated vision could be tested. The tool we have developed to achieve this is called WepSIM and it provides the view of an elemental processor together with a microprogrammed subset of the MIPS instruction set. In addition, WepSIM is flexible enough to be adapted to other instruction sets or hardware components (e.g., ARM or x86). Third, we want to extend the activities of our university courses, labs, and lectures (fixed hours in a fixed place), so that students may learn by using their mobile device at any location, and at any time during the day. This paper presents how WepSIM has improved the teaching of Computer Architecture courses by empowering students with a more dynamic and guided learning process. In this paper, we show the results obtained during the experience of using the simulator in the Computer Structure course of the Bachelor's Degree in Computer Science and Engineering, University Carlos III of Madrid.
The work presented in this paper is on reconfigurable accelerators for the implementation of iterative computations and loops that form the core computations of applications like those in digital signal processing and...
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ISBN:
(纸本)9781728199382
The work presented in this paper is on reconfigurable accelerators for the implementation of iterative computations and loops that form the core computations of applications like those in digital signal processing and machine learning. The accelerators become computation engines of an embedded system that can be reconfigured by an embedded processor for handling various kernels of embedded applications. This paper presents our MicroProgramed Configurable Accelerator (iMPAC) architecture and compares implementing a kernel (here a matrix multiplication) on this architecture with a) a program running of an embedded processor and b) with a hardwired controller accelerator. Our prototyping on an FPGA shows very little penalty in terms of energy consumption and required clock cycles when compared with the latter, and significant improvement of both energy and timing when compared with the former. At the same time, we have the programming flexibility of the former.
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