In a previous paper, it was shown that the presence of a combinatorial shifter in the data paths of a user microprogrammable general purpose computer could be used for fast fixed-point multiplication if a unique micro...
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In a previous paper, it was shown that the presence of a combinatorial shifter in the data paths of a user microprogrammable general purpose computer could be used for fast fixed-point multiplication if a unique microsubroutine was created for each required multiplier. A sixth-order direct form IIR digital filter was implemented via this technique. This work has been extended, so as to produce a tenth-order LPC k-parameter lattice synthesizer software system which executes in about 60% real time. The remaining CPU time may be allocated for k-parameter manipulation, as in synthesis-by-rule aAgorithms, or for unrelated computation. The approach used is novel since it involves dynamic analysis of k-parameters and creation of the microsubroutines required for synthesis during each pitch period. The results suggest that a high speed shifter embedded in an otherwise conventional micromachine architecture is Useful for practical, real-time digital signal processing applications.
A non-traditional microprogramming language and its development using a compiler-compiler are described. An idea of the synergism that can develop between more user-oriented microprogramming tools, well-organized hard...
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A non-traditional microprogramming language and its development using a compiler-compiler are described. An idea of the synergism that can develop between more user-oriented microprogramming tools, well-organized hard- ware architecture, and compiler-compiler syntax structure is presented. Considering the characteristics of the resulting product, the effort involved in this implementation methodology seems to have been well-spent.
Fault tolerant microprocessor-based systems are traditionally synonymous to hardware redundancy. A technique that considers error avoidance due to fault processor or software fault tolerance is presented to provide a ...
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Fault tolerant microprocessor-based systems are traditionally synonymous to hardware redundancy. A technique that considers error avoidance due to fault processor or software fault tolerance is presented to provide a more practical implementation of a system. The technique is a very effective tool for the detection of faults in the processor or the program by means of periodic validation of the processor status. The technique is a reliable and cost-effective software tool.
This paper proposes an architecture for implementing in VLSI technology VLC (variable length code) for video coding. The objective of this architecture is to optimize the memory size while maintaining a low access tim...
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This paper proposes an architecture for implementing in VLSI technology VLC (variable length code) for video coding. The objective of this architecture is to optimize the memory size while maintaining a low access time to VLC words. The architecture is based on reordering codes and addressing tables by means of hashing methods. The hardware implementation of hash functions is solved using a flexible datapath controlled by microprogramming techniques. The number of clock cycles to obtain the codes as well as both estimated area and clock period is used to evaluate the performance of the proposed architecture.
A machine‐dependent, microprogramming language for use on the Burroughs B1700 range of computers is described. It is a relatively high‐level language, containing a data‐structure definition facility and a control s...
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Firmware security in edge-enabled IoT devices is crucial, but existing methods struggle to balance strong protection with realistic hardware trust assumptions, device privacy, nontraceability, and resilience against a...
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Firmware security in edge-enabled IoT devices is crucial, but existing methods struggle to balance strong protection with realistic hardware trust assumptions, device privacy, nontraceability, and resilience against attacks. This article addresses these challenges by introducing a novel permutation-based firmware attestation mechanism. Our method leverages edge servers as verifiers, low-cost memory, randomized permutations, and avalanche criteria for optimized security and efficiency. Rigorous formal and informal security analysis, coupled with performance evaluation, demonstrates superior performance against various attacks, achieving over 90% detection probability and effectively mitigating both remote and mobile software attacks. These results demonstrate the significant potential of our approach for enhancing firmware security in edge-enabled IoT devices.
System-on-Chips (SoCs) are ubiquitously used as smart devices with heterogeneous components embedded within them. The effective functioning of a system depends on Intellectual Property (IP) and firmware updates, which...
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System-on-Chips (SoCs) are ubiquitously used as smart devices with heterogeneous components embedded within them. The effective functioning of a system depends on Intellectual Property (IP) and firmware updates, which enhance performance and reliability and rectify vulnerabilities throughout the lifespan of any SoC. However, malicious logic intrusion by intruders can compromise the system's efficacy at the design phase of Internet of Things (IoT) applications. The proposed robust unified security framework efficiently streamlines the identification of hardware Trojans and secure firmware updates of the IPs in all intricate and heterogeneous SoCs without the need for the golden reference model. In the post-silicon validation technique, the authentication protocol utilizes the device-specific fingerprint of a Physical Unclonable Function (PUF) to authenticate the IPs. An enhanced Balanced Anderson Arbiter PUF (BAA-PUF) integrating two sources of randomness is physically implemented in ZCU104 MPSoC to generate 256 bits. The parameters of BAA-PUF are determined by majority voting and are close to the ideal value. The average execution time for identifying the Trojan with the proposed framework is found to be 40.184 ms. Two metrics have been introduced to demonstrate the efficacy of the proposed framework, namely, utilization scale, which illustrates the impact of Trojans on the resource utilized and digest uniqueness, which demonstrates the presence of Trojans and ranges from 45.3% to 55%. The performance of the authentication protocol is also validated based on computation and communication costs. The authentication protocol is analyzed using the formal technique, employing Burrows-Abadi-Needham (BAN) logic and informal methods to confirm its robustness against hardware-based attacks.
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