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Area and power-efficient variable-length fast Fourier transform for MR-OFDM physical layer of IEEE 802.15.4-g

IET COMPUTERS AND DIGITAL TECHNIQUES 2020年第5期14卷 193-200页

作者： Kumar, Ganjikunta Ganesh Sahoo, Subhendu K. Sreenidhi Inst Sci & Technol Dept ECE Hyderabad India BITS Pilani Hyderabad Campus Dept EEE Hyderabad India

The authors present a novel 16/32/64/128-point single-path delay feedback pipeline fast Fourier transform (FFT) architecture targeting the multi-rate and multi-regional orthogonal frequency division multiplexing (MR-OFDM) physical layer of IEEE 802.15.4-g. The proposed FFT architecture employs a mixed-radix algorithm to significantly reduce the number of complex multipliers. It utilises a configurable complex constant multiplier structure instead of a fixed constant multiplier to efficiently conduct W-32, W-64, and W-128 twiddle factor multiplication. A hardware-sharing mechanism has also been formulated to reduce the memory space requirements of the proposed 16/32/64/128-point FFT computation scheme. The proposed design is implemented in Xilinx Virtex-5 and Altera's field-programmable gate array devices. For the computation of 128-point FFT, the proposed mixed-radix FFT architecture significantly reduces the hardware cost in comparison with existing FFT architecture. The proposed FFT architecture is also implemented by adopting the 90 nm complementary metal-oxide-semiconductor technology with a supply voltage of 1 V. Post-synthesis results reveal that the design is efficient in terms of gate count and power consumption, compared to earlier reported designs. The proposed variable-length FFT architecture gate count is 22.3K and consumes 3.832 mW, while the word-length is 12-bits and can be efficiently useful for the IEEE 802.15.4-g standard.

关键词： OFDM modulation fast Fourier transforms field programmable gate arrays power consumption digital arithmetic CMOS logic circuits Zigbee power-efficient variable-length fast Fourier transform MR-OFDM physical layer IEEE 802 15 4-g standard multirate orthogonal frequency division multiplexing physical layer multiregional orthogonal frequency division multiplexing physical layer mixed-radix algorithm configurable complex constant multiplier structure W-128 twiddle factor multiplication Altera field-programmable gate array devices mixed-radix FFT architecture variable-length FFT architecture gate count post-synthesis hardware cost reduction Xilinx Virtex-5 16-32-64-128-point single-path delay feedback pipeline fast Fourier transform architecture W-64 twiddle factor multiplication W-32 twiddle factor multiplication hardware-sharing mechanism memory space requirement reduction 128-point FFT complementary metal-oxide-semiconductor technology power consumption area-efficient variable-length fast Fourier transform size 90 0 nm voltage 1 0 V power 3 832 mW word length 12 bit

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Generalized fast mixed-radix algorithm for the computation of forward and inverse MDCTs

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SIGNAL PROCESSING 2012年第2期92卷 363-373页

作者： Gui, Z. G. Ge, Y. Zhang, D. Y. Wu, J. S. Nanjing Univ Dept Elect Sci & Engn Nanjing 210093 Peoples R China N Univ China Natl Key Lab Elect Measurement Technol Taiyuan 030051 Peoples R China Nanjing Univ Dept Informat Sci & Engn Nanjing 210093 Peoples R China Southeast Univ Lab Image Sci & Technol Nanjing 210096 Peoples R China

This paper presents a generalized mixed-radix decimation-in-time (DIT) fast algorithm for computing the modified discrete cosine transform (MDCT) of the composite lengths N=2 x q(m), m >= 2, where q is an odd positive integer. The proposed algorithm not only has the merits of parallelism and numerical stability, but also needs less multiplications than that of type-IV discrete cosine transform (DCT-IV) and type-II discrete cosine transform (DCT-II) based MDCT algorithms due to the optimized efficient length-(N/q) modules. The computation of MDCT for composite lengths N=q(m) x 2(n), m >= 2, n >= 2, can then be realized by combining the proposed algorithm with fast radix-2 MDCT algorithm developed for N=2(n). The combined algorithm can be used for the computation of length-12/36 MDCT used in MPEG-1/-2 layer III audio coding as well as the recently established wideband speech and audio coding standards such as G.729.1, where length-640 MDCT is used. The realization of the inverse MDCT (IMDCT) can be obtained by transposing the signal flow graph of the MDCT. (C) 2011 Elsevier B.V. All rights reserved.

关键词： Modified discrete cosine transform mixed-radix algorithm Fast algorithm

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Compact and high-throughput parameterisable architectures for memory-based FFT algorithms

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IET CIRCUITS DEVICES & SYSTEMS 2019年第5期13卷 696-703页

作者： Valencia, Daniel Alimohammad, Amirhossein San Diego State Univ Dept Elect & Comp Engn 5500 Campanile Dr San Diego CA 92182 USA

Designers must carefully choose the best-suited fast Fourier transform (FFT) algorithm among various available techniques for the custom implementation that meets their design requirements, such as throughput, latency, and area. This article, to the best of authors' knowledge, is the first to present a compact and yet high-throughput parameterisable hardware architecture for implementing different FFT algorithms, including radix-2, radix-4, radix-8, mixed-radix, and split-radix algorithms. The designed architectures are fully parameterisable to support a variety of transform lengths and variable word-lengths. The FFT algorithms have been modelled and simulated in double-precision floating-point and fixed-point representations using authors' custom-developed library of numerical operations. The designed FFT architectures are modelled in Verilog hardware description language and their cycle-accurate and bit-true simulation results are verified against their fixed-point simulation models. The characteristics and implementation results of various FFT architectures on a Xilinx Virtex-7 FPGA are presented. Compared to recently published works, authors' memory-based FFT architectures utilise less reconfigurable resources while maintaining comparable or higher operating frequencies. The ASIC implementation results in a standard 45-nm CMOS technology are also presented for the designed memory-based FFT architectures. The execution times of FFTs on a workstation and a graphics processing unit are compared against authors' FPGA implementations.

关键词： hardware description languages fast Fourier transforms application specific integrated circuits field programmable gate arrays floating point arithmetic CMOS memory circuits CMOS logic circuits reconfigurable architectures discrete Fourier transforms signal flow graphs memory architecture logic design integrated circuit design fixed point arithmetic high-throughput parameterisable architectures split-radix algorithms regular structures symmetries properties signal flow graphs fixed-point representations Verilog hardware description language fixed-point simulation models compact-throughput parameterisable architectures fast Fourier transform algorithm discrete FFT algorithms radix-2 algorithm radix-4 algorithm radix-8 algorithm mixed-radix algorithm double-precision floating-point representation author custom-developed library numerical operations synthesisable FFT architectures bit-true simulation cycle-accurate simulation Xilinx Virtex-7 FPGA author memory-based FFT architectures reconfigurable resources ASIC standard CMOS technology size 45 nm

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