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A 17.5-fJ/bit Energy-Efficient Analog SRAM for mixed-signal processing

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2017年第10期25卷 2714-2723页

作者： Lee, Jinsu Shin, Dongjoo Kim, Youchang Yoo, Hoi-Jun Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon 305701 South Korea

An energy-efficient analog SRAM (A-SRAM) is proposed to eliminate redundant analog-to-digital (A/D) and digital-to-analog (D/A) conversion in mixed-signal systems, such as neuromorphic chips and neural networks. D/A conversion is integrated into the SRAM readout by charge sharing of the proposed split bitline (BL). Also, A/D conversion is integrated into the SRAM write operation with the successive approximation method in the proposed input-output block. Also, a configurable SRAM bitcell array is proposed to allocate the converted digital data without unfilled bitcells. The multirow access decoder selects multiple bitcells in a single column and configures the bitcell array by controlling the BL switches to split BLs. The proposed A-SRAM is implemented using the 65-nm CMOS technology. It achieves 17.5-fJ/bit energy-efficiency and 21-Gbit/s throughput for the analog readout, which are 64% and 1.3 times better than those of the conventional SRAM followed by a digital-to-analog converter (DAC). Also, the area is reduced by 91% compared with the conventional SRAM with analog-to-digital converter (ADC) and DAC.

关键词： ADC analog memory DAC mixed-signal processing SRAM

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A 17.5 fJ/bit Energy-efficient Analog SRAM for mixed-signal processing

A 17.5 fJ/bit Energy-efficient Analog SRAM for Mixed-signal ...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Lee, Jinsu Shin, Dongjoo Kim, Youchang Yoo, Hoi-Jun Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon South Korea

ISBN: (纸本)9781479953417

An energy-efficient analog SRAM (A-SRAM) is proposed to eliminate redundant analog-to-digital (A/D) and digital-to-analog (D/A) conversions in the mixed-signal processing such as a biomedical and a neural network applications. The D/A and the A/D conversion are integrated into the SRAM readout by the charge sharing of the proposed split bit-line (BL) and the SRAM write by the successive approximation method, respectively. And a data structure is newly proposed to allocate each bit of the input data to the binary-weighted bit-cell array. The proposed A-SRAM is implemented using 65 nm CMOS technology. As a result, it achieves 17.5 fJ/bit read energy-efficiency and 21 Gbit/s read throughput, which are 54% lower and 1.3x higher than the conventional SRAM. Also, the area is reduced by 31% compared to the conventional SRAM with ADC and DAC.

关键词： analog memory SRAM mixed-signal processing ADC DAC energy-efficiency area-efficiency

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Towards a Standard mixed-signal Parallel processing Architecture for Miniature and Microrobotics

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JOURNAL OF RESEARCH OF THE NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY 2014年第5期119卷 529-539页

作者： Sadler, Brian M. Hoyos, Sebastian Army Res Lab Adelphi MD 20783 USA Texas A&M Univ Dept Elect & Comp Engn College Stn TX 77843 USA

The conventional analog-to-digital conversion (ADC) and digital signal processing (DSP) architecture has led to major advances in miniature and micro-systems technology over the past several decades. The outlook for these systems is significantly enhanced by advances in sensing, signal processing, communications and control, and the combination of these technologies enables autonomous robotics on the miniature to micro scales. In this article we look at trends in the combination of analog and digital (mixed-signal) processing, and consider a generalized sampling architecture. Employing a parallel analog basis expansion of the input signal, this scalable approach is adaptable and reconfigurable, and is suitable for a large variety of current and future applications in networking, perception, cognition, and control.

关键词： analog-to-digital conversion communications control mixed-signal architecture mixed-signal processing perception robotics sensing signal processing

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Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

Integration of Si-CMOS embedded photo detector array and mix...

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Conference on Semiconductor Photodetectors

作者： Kim, DD Thomas, M Brooke, MA Jokerst, NM Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

ISBN: (纸本)0819452610

Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5mum n-well Si-CMOS process and the embedded PNP BJT PD has a pixel size of 8mum by 8mum. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma (DeltaSigma) oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

关键词： Si-CMOS circuit embedded photo detector mixed-signal processing delta-sigma analog-to-digital converter

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A Fully Dynamic Multi-Mode CMOS Vision Sensor With mixed-signal Cooperative Motion Sensing and Object Segmentation for Adaptive Edge Computing

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2020年第6期55卷 1684-1697页

作者： Zhong, Xiaopeng Law, Man-Kay Tsui, Chi-Ying Bermak, Amine Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI Inst Microelect Macau Peoples R China Hamad Bin Khalifa Univ Informat & Comp Technol Div Coll Sci & Engn Doha Qatar

This article presents a low-power multi-mode CMOS vision sensor with mixed-signal in-sensor computation capabilities targeting the next-generation wireless sensing applications. To support the always-on and scene-adaptive edge computing scenarios with low power and low bandwidth, the sensor is reconfigurable for three operation modes, namely: 1) motion sensing (MS);2) object segmentation (OS);and 3) full imaging (FIM). A mixed-signal cooperative scheme of frame differencing (FD) and background subtraction (BS) is proposed to achieve high-accuracy MS with varying object sizes and speeds. The mixed-signal BS-based OS can minimize both object localizing and imaging efforts for object analysis upon motion triggering, while FIM enables complete scene recording for the identified object of interest. The complete CMOS vision sensor is implemented through reconfigurable and fully dynamic mixed-signal processing at both pixel and column levels cooperatively to achieve low power and compact area. Fabricated in a 0.18-mu m CMOS, the 256 x 216 chip prototype achieves the cooperative MS with only 2.36 mu W at 15 frames/s, when composed of 14 FD frames (147 nJ/frame) and 1 BS frame (302 nJ/frame). The OS mode consumes 1.44 similar to 2.04 mu J/frame at 0%similar to 100% object occupancy, linearly corresponding to 41%similar to 16% power saving when compared with the conventional digital OS. The FIM mode operates with only 1.41 mu J/frame for complete scene recording. The achieved energy efficiencies for all operation modes compare favorably with the state of the art.

关键词： Vision sensors Bandwidth Edge computing Wireless sensor networks Program processors Object segmentation Background subtraction (BS) CMOS vision sensor cooperative motion sensing (MS) edge computing frame differencing (FD) fully dynamic in-sensor computation mixed-signal processing object segmentation (OS) wireless sensor networks (WSNs)

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Multichannel 2-D Direction Finding Based on Differential Amplitude Detection

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IEEE SENSORS JOURNAL 2015年第9期15卷 5064-5070页

作者： Mitrovic, Nemanja M. Ponjavic, Milan M. Univ Belgrade Sch Elect Engn Belgrade 11120 Serbia

This paper looks toward theoretical and practical aspects of a new 2-D direction finding method. It promotes a new idea for multichannel azimuth estimation based on amplitude difference of a signal acquired on adjacent antennas. The essence of the method is a simple hardware consisting of small size microwave (7-19 GHz) antennas equipped with amplitude detectors, frequency synthesizer, low power mixed-signal processing hardware, and a small and efficient firmware. Significant advantage of the proposed multichannel approach is simplified detection of infinitely close incoming signals with no theoretical limitation in their number. Different calibration types provide detection nearly undependable of frequency in whole bandwidth of interest. With the aim to complete image of the proposed method, probability of detection and azimuth estimation precision are discussed in this paper. Precision of azimuth estimation is in the range of 5 degrees for encapsulated antennas or 10 degrees in other cases. Proposed method can find application in various engineering fields, including geosciences field research, wireless communications, radio-monitoring, security service, and so on.

关键词： Direction of arrival estimation HF wideband antennas mixed-signal processing

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IoT Cloud-Edge Reconfigurable mixed-signal Smart Meter Platform for Arc Fault Detection

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IEEE INTERNET OF THINGS JOURNAL 2023年第2期10卷 1682-1695页

作者： Wu, Ya-Jie Brito, Ricardo Choi, Wai-Hei Lam, Chi-Seng Wong, Man-Chung Sin, Sai-Weng Martins, Rui Paulo Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau State Key Lab Internet Things Smart City Macau Peoples R China Univ Macau Fac Sci & Technol State Key Lab Internet Things Smart City Guangdong Hong Kong Macau Joint Lab Smart Cities Macau Peoples R China Univ Macau Fac Sci & Technol Dept Elect & Comp Engn Macau Peoples R China Univ Macau Fac Sci & Technol Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Fac Sci & Technol State Key Lab Analog & Mixed Signal VLSI State Key Lab Internet Things Smart CityGuangdon Macau Peoples R China Univ Lisbon Inst Super Tecn P-1649004 Lisbon Portugal

Smart meter monitors electricity consumption through modern metering devices connected to the Internet via Internet of Things (IoT) technology, which can provide intelligent and fast applications on-site such as arc fault protection based on nonintrusive monitoring load classification with fast safety responses for varying electric loads. Traditional three, four, and five layers of the IoT architecture cannot support such fast responses under loading variation. This article aims to propose six layers of IoT Cloud-Edge Infrastructure equipped with a reconfigurable mixed-signal controller as a smart meter platform for adaptation to different environments and, for example, deal with fast arc fault detection corresponding to different load characteristics. Such an architecture can reduce the processing time for safety, reduce bandwidth for communication, improve arc detection accuracy under different loading environments, and lower the overall computation cost.

关键词： Internet of Things Cloud computing Computer architecture Fault detection Edge computing Smart meters Safety Arc fault detection cloud computing edge computing Internet of Things (IoT) mixed-signal processing smart meters

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A 4-Bit mixed-signal MAC Macro With One-Shot ADC Conversion

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2023年第9期58卷 2648-2658页

作者： Yang, Xiangxing Sun, Nan Univ Texas Austin Dept Elect & Comp Engn Austin TX 78712 USA pSemi Corp Austin TX 78704 USA Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China

This work proposes a charge-domain 4-bit multiply-and-accumulate (MAC) macro for deep neural network (DNN) accelerators. The proposed macro requires only 1 analog to digital converter (ADC) operation for the entire 512 4 x 4 b MAC. The one-shot conversion is achieved by sampling partial MAC products onto properly sized capacitors in the SAR ADC. As a result, all MAC operations are finished in the charge domain by the end of ADC sampling, allowing only 1 analog-to-digital (A/D) conversion per multi-bit MAC. To further reduce energy consumption, the SAR ADC features bypass window-based conversion skipping and embedded rectified linear unit (ReLU) activation. The prototype is fabricated in 65-nm complementary metal-oxide semiconductor (CMOS) process with an active area of 0.18 mm(2). The measured throughput is 56.3 giga operations per second (GOPS) with 345.3 mu W power consumption, achieving 164 tera operations per watt (TOPS/W) energy efficiency.

关键词： In-memory computing (IMC) mixed-signal processing multi-bit neural networks switched-capacitors (SC)

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An In-Memory-Computing Charge-Domain Ternary CNN Classifier

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2023年第5期58卷 1450-1461页

作者： Yang, Xiangxing Zhu, Keren Tang, Xiyuan Wang, Meizhi Zhan, Mingtao Lu, Nanshu Kulkarni, Jaydeep P. P. Pan, David Z. Z. Liu, Yongpan Sun, Nan Univ Texas Austin Dept Elect & Comp Engn Austin TX 78712 USA Peking Univ Inst Artificial Intelligence Beijing 100871 Peoples R China Peking Univ Sch Integrated Circuit Beijing 100871 Peoples R China Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China

The article presents a charge-domain computing ternary neural network (TNN) classifier with a complete four-layer neural network (NN) on a chip. The proposed ternary network provides 1.5-b resolution (0/+1/-1) for weights and activations, leading to 3.9 x fewer operations (OPs) per inference than binary neural network (BNN) for the same Modified National Institute of Standards and Technology (MNIST) accuracy. The 1.5-b multiply-and-accumulate (MAC) is implemented by V-CM- based capacitor switching scheme, which inherently benefits from the reduced signal swing on the capacitive digital-to-analog converter (CDAC). Also, the V-CM-based MAC introduces sparsity during training, resulting in a lower switching rate. The prototype is fabricated in a 40-nm LP CMOS process with an active area of 0.98 mm(2), operates at 549 frames/s (FPS), and consumes 96 mu W. With all OPs on the chip, it achieves 97.1% MNIST accuracy with 0.18 mu J per classification, which is the smallest to our knowledge for comparable MNIST classification accuracy.

关键词： Capacitors Computer architecture Voltage Switches Registers Synapses Neurons In-memory computing mixed-signal processing switched capacitors (SCs) ternary neural networks (TNNs)

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Digital Compensation of Cross-Modulation Distortion in Software-Defined Radios

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IEEE JOURNAL OF SELECTED TOPICS IN signal processing 2009年第3期3卷 348-361页

作者： Zou, Qiyue Mikhemar, Mohyee Sayed, Ali H. Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90095 USA

The wideband RF receiver in a software-defined radio (SDR) system suffers from the nonlinear effects caused by the front-end analog processing. In the presence of strong blocker (interference) signals, such nonlinearities introduce severe cross modulation over the desired signals. This paper investigates how the cross-modulation distortion can be compensated for by using digital processing techniques. In the proposed solution, the SDR scans the wide spectrum and locates the desired signal and strong blocker signals. After down-converting these signals separately to the baseband, the baseband processor processes them jointly to mitigate the cross-modulation interferences. As a result, the sensitivity of the wideband RF receiver to the nonlinearity impairment can be significantly lowered, simplifying the RF and analog circuitry design in terms of implementation cost and power consumption. The proposed approach also demonstrates how mixed-signal, i.e., joint analog and digital, processing techniques play a critical role in the emerging SDR and cognitive radio technologies.

关键词： Channel estimation cross modulation mixed-signal processing nonlinearity orthogonal frequency division multiplexing (OFDM) software-defined radio (SDR) wireless communication

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